• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

• Journal of the Korea Convergence Society
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• v.11 no.4
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• pp.157-163
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• 2020

This paper is a product design convergence study to improve the aesthetic quality of CIGS solar cells for utilizing urban living structures, identifying problems of existing solar cell panels and drawing expert aesthetic elements for improving CIGS solar cells through survey and [Group discussion of experts] based on aesthetic elements of product design. Out of the aesthetic elements derived, the top three models of the product design process were 'environmental harmonization', 'pattern balance', and 'period universality' to derive the design and assembly design of the CIGS solar cell module for improving aesthetic quality, and applied to apartments, veranda, windows, and streetcar through product simulation. This study is suitable for applying aesthetic and CIGS solar cell function later to actual urban living structure, and future research direction needs to be studied on various patterns and structural design development of design.

• Journal of Internet Computing and Services
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• v.13 no.1
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• pp.125-134
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• 2012

As the social networking service (SNS), Facebook, and Cyworld, is developing, the social network game and social business commerce based on this service is activated. Especially, the Social Network Game (SNG) is getting explosive interests and it becomes popular, because it is small scale and user can enjoy the game among close friends. The market for this game is getting larger every year, but still it has some limitations in developing the game. Especially, the current game engine is aiming for developing online or console game, and there is no exclusive game engine for developing SNG. Therefore, it takes lots of time for developing SNG with this game engine. In this paper, we described a design and development of the game engine optimized for developing SNG, which not only adapts the main characteristics of the previous game engine, but also considers the specific characteristics of the SNG. The engine also supports map for the simulation game that is the most popular game in SNG, and also provides modules and tools for developing character animation easily. The evaluation standard for the performance of the game engine is the output generation speed of image, text and character. And the results showed reasonable output speed for developing the SNG in generation of image, text, and character.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• The Journal of the Korea Contents Association
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• v.11 no.12
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• pp.78-87
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• 2011

A variety of intelligent application using the sensor network system is being studied. In general, the sensor network consists of nodes which equipped with a variety of sensing module and is utilized to collect environment information. Recently, the demands of multimedia data are increasing due to the demands of more detailed environmental monitoring or high-quality data. In this paper, we overcome the limitations of low bandwidth in Zigbee-based sensor networks and propose a routing algorithm for real-time multimedia data transmission. In the previously proposed algorithm for multimedia data transmission occurs delay time of routing setup phase and has a low data transmission speed due to bandwidth limitations of Zigbee. In this paper, we propose the hybrid routing algorithm that consist of Zigbee and Bluetooth and solve the bandwidth problem of existing algorithm. We also propose the disjointed multipath setup algorithm based on competition that overcome delay time of routing setup phase in existing algorithm. To evaluate the superiority of the proposed algorithm, we compare it with the existing algorithm. Our experimental results show that the latency was reduced by approximately 78% and the communication speed is increased by approximately 6.9-fold.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.4
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• pp.811-817
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• 2009

The rapid growth of network based IT systems has resulted in continuous research of security issues. Probe intrusion detection is an area of increasing concerns in the internet community. Recently, a number of probe intrusion detection schemes have been proposed based on various technologies. However, the techniques, which have been applied in many systems, are useful only for the existing patterns of probe intrusion. They can not detect new patterns of probe intrusion. Therefore, it is necessary to develop a new Probe Intrusion Detection technology that can find new patterns of probe intrusion. In this paper, we proposed a new network based probe intrusion detector(NePID) using anomaly traffic analysis and fuzzy cognitive maps that can detect intrusion by the denial of services attack detection method utilizing the packet analyses. The probe intrusion detection using fuzzy cognitive maps capture and analyze the packet information to detect syn flooding attack. Using the result of the analysis of decision module, which adopts the fuzzy cognitive maps, the decision module measures the degree of risk of denial of service attack and trains the response module to deal with attacks. For the performance evaluation, the "IDS Evaluation Data Set" created by MIT was used. From the simulation we obtained the max-average true positive rate of 97.094% and the max-average false negative rate of 2.936%. The true positive error rate of the NePID is similar to that of Bernhard's true positive error rate.

• Journal of Satellite, Information and Communications
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• v.7 no.3
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• pp.16-21
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• 2012

Recently, an importance of culture industry has been emphasized through an increased income level, spare time and changed values of modern people. And demands of the performance, arts, exhibit are steadily being increased. However the stage equipment depends on foreign manufactures on account of the inactive domestic technical skills. Especially in the lighting direction part, it is essential to control the lighting source and detect the moving line of actors but it generally uses the manual control type and realization of actor's moving line regardless of existing IT-based technologies. Also the system operation of existing sensor-based tracking and detecting technologies depends on the main lighting source of the stage. Therefore, this paper proposed LED lighting control system using the variable FOV and multi sensor-based tracking algorithm, which are possible to efficiently track the stage actors and direct the stage lights. Also we demonstrated the practicality and possibility of realization through the integrated experiment of the proposed system and implementation of the salient hardware, software. Additionally, the usefulness of proposed system was demonstrated using performance simulations and actual measurements of implemented sensor output.

• Journal of Satellite, Information and Communications
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• v.7 no.3
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• pp.99-104
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• 2012

The United States will proceed with the effort to modernize the GPS system, and one of its main content is to provide L5 signal. L5 will be transmitted in a radio band reserved exclusively for aviation safety services. And, L5, in combination with L1, will improve the position accuracy via ionospheric correction and robustness via signal redundancy. However, The acquisition processing time of L5 takes longer than that of L1 as the code length of L5 is 10 times longer than that of L1. To reduce this acquisition processing time, a higher number of correlators in the aquisition module should be used. However, there is a problem that this causes increase in the complexity of the correlator configuration and the computation power. So, in this paper, we propose L5 signal tracking scheme using tracking results in the GPS L1/L5 receiver. The proposed scheme could reduce the hardware complexity as the GPS L5 signal acquisition module is not needed, and provide fast and stable tracking of L5 signal by aiding L1 tracking results such as PRN, the code phase synchronization, and the Doppler frequency. The feasibility of the proposed scheme is demonstrated through simulation results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.42-48
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• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.