• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.6
• /
• pp.1250-1259
• /
• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.414-422
• /
• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.88-90
• /
• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of IKEEE
• /
• v.26 no.4
• /
• pp.577-583
• /
• 2022

Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.4
• /
• pp.499-508
• /
• 1995

Domain Analysis is an activity to identify commonalities and variabilities which similar application areas in order to reuse analyzed information easily in new software construction. Most of domain analysis output is represented by various diagrams without common standard, and its manual reuses result in low reusability. Domain analysis language can be used to represent domain analysis information and make it possible to automate reuse and test the specifications. In this paper we designed and implemented a processor to reuse domain analysis information represented by domain analysis language and applied our approach to a rental domain and got new specification instances. In addition, we compared reuse of a data flow diagramming tool with reuse of a domain information processor and found combining and found combining of each approach can increase the reusability of both.

• Annual Conference on Human and Language Technology
• /
• 2019.10a
• /
• pp.87-92
• /
• 2019

본 논문에서는 기계 독해를 이용한 웹 기반 오픈 도메인 한국어 질의응답 시스템에 대하여 서술한다. 하나의 사용자 질의에 대하여, 본 논문에서 제안된 시스템은 기 존재하는 검색 엔진을 이용하여 실시간으로 최대 1,500 개의 문서를 기계 독해 방식으로 분석하고, 각 문서별로 얻어진 답을 종합함으로써 최종 답변을 도출한다. 실험 결과, 제안된 시스템은 평균적으로 2초 이내의 실행 시간을 보였으며, 사람과 비교하여 86%의 성능을 나타내었다. 본 논문에서 제안된 시스템의 데모는 http://nlp-api.kakao.com에서 확인 가능하다.

• Journal of Satellite, Information and Communications
• /
• v.6 no.1
• /
• pp.86-96
• /
• 2011

In this paper we propose a Pre-rake system applied with a frequency domain equalizer in TDD/CDMA multi-code transmission. The Pre-rake system has been well known technique in TDD/CDMA to make a receiver simple. However, it still has residual losses of path diversity and signal to noise ratio (SNR). However, gathering all the residual paths demands an additional hardware such as a rake combiner at the receiver. For the reason Pre/Post-rake system has already been proposed at up/downlink correlated channel conditionunder the assumption of noisier channel. There is a trade-off between the first purpose of Pre-rake that makes hardware simple at the receiver and the performance improvement. From the point the frequency domain equalizer (FDE) can be considered in Pre/Post-rake to supply the receiver with the flexible equalizing methods with rather reduced complexity compared with time domain rake combiner or equalizers. Pre-rake itself increases the number of multipath, which results from the convolution of Pre-rake filter and wireless channel, and FDE must be well matched to Pre/Post-rake, while it considers the relationship of hardware complexity and the performance. In this paper, the Pre-rake/Post-FDE system is introduced at TDD/CDMA multi-code transmission. In addition, the cyclic prefix reduction method in the proposed system is introduced, and the theoretical analysis to the proposed system is given by assuming Gaussian approximation, and finally the numerical simulation results are provided.

• Phonetics and Speech Sciences
• /
• v.12 no.2
• /
• pp.29-37
• /
• 2020

Recently, the neural network-based deep learning algorithm has dramatically improved performance compared to the classical Gaussian mixture model based hidden Markov model (GMM-HMM) automatic speech recognition (ASR) system. In addition, researches on end-to-end (E2E) speech recognition systems integrating language modeling and decoding processes have been actively conducted to better utilize the advantages of deep learning techniques. In general, E2E ASR systems consist of multiple layers of encoder-decoder structure with attention. Therefore, E2E ASR systems require data with a large amount of speech-text paired data in order to achieve good performance. Obtaining speech-text paired data requires a lot of human labor and time, and is a high barrier to building E2E ASR system. Therefore, there are previous studies that improve the performance of E2E ASR system using relatively small amount of speech-text paired data, but most studies have been conducted by using only speech-only data or text-only data. In this study, we proposed a semi-supervised training method that enables E2E ASR system to perform well in corpus in different domains by using both speech or text only data. The proposed method works effectively by adapting to different domains, showing good performance in the target domain and not degrading much in the source domain.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.5
• /
• pp.691-700
• /
• 1995

Most fractal image codings using fractal concept require long encoding time because a large amount of computation is needed to find an optimal affine transformation point. Such a problem can be solved by designing a block classifier fitted to characteristics of image blocks. In general, it is possible to predict more precise and various types of blocks in frequency domain than in spatial domain. In this paper, we propose a block classifier to predict the block type using characteristics of DCT(Discrete Cosine Transform). This classifier has merits to enhance the quality of decoded images as well as to reduce the encoding time meeting fractal features. AC coefficient values in frequency domain make it possible to predict various types of blocks. As the results, the number of comparisons between a range block and the correspoding domain blocks to reach an optimal affine transformation point can be reduced. Specially, signs of DCT coefficients help to find the optimal affine transformation point with only two isometric transformations by eliminating unnecessary isometric transformations among eight isometric transformations used in traditional fractal codings.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.378-384
• /
• 2013

In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a $0.25{\mu}m$ 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to $150^{\circ}C$. The area and power consumption of the fabricated temperature sensor are $130{\times}390{\mu}m^2$ and $868{\mu}W$, respectively.