• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.6
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• pp.665-674
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• 2001

In this paper, a reduced complexity fillet to simultaneously suppress the blocking and ringing artifacts of compressed video sequence is addressed. A new one dimensional regularized function to incorporate the smoothness to its neighboring pixels into the solution is defined, resulting in very low complexity filter The proposed regularization function consists of two sub-functions that combine local data fidelity and local smoothing constraints. The regularization parameters to control the trade-off between the local fidelity to the data and the smoothness are determined by available overhead information in decoder, such as maroc-block type and quantization step size. In addition, the regularization parameters are designed to have the limited range and stored as look-up-table, and therefore, the computational cost to determine the parameters can be reduced. The experimental results show the capability and efficiency of the proposed algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.340-351
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• 2010

This paper presented compact CW sub-THz imaging system using the terahertz transmitter(Tx) that generates 0.34 THz electromagnetic wave based on electronic device. Using 0.34 THz electromagnetic wave generated by Tx, we measured transmitting terahertz wave magnitude and phase information respectively with terahertz receiver(Rx) based on sub harmonic mixer. This paper measured and compared images of several samples to obtain better imaging results by changing time delay and step distance of scanning stage which affect image resolution. Also, through the imaging measurement of various samples, we were able to assure possibility of application of terahertz wave.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1744-1749
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• 2013

Acoustic feedback is perceived as whistling or howling, which is a major complaint of hearing-aids users. Acoustic feedback cancellation is important in hearing-aids because acoustic feedback degrades performance of the hearing aid device by reducing maximum insertion gain. Adaptive systems for estimate acoustic feedback path and feedback suppression algorithms have been proposed in order to solve this problem. A typical feedback cancellation algorithm is LMS(least mean squares) because of its computational efficiency. However it has problem of convergence performance in high correlated input signal. In this paper, we propose a new variable step-size normalized LMS(least mean squares) algorithm using VAD(voice activity detection) to overcome the limitation of the LMS algorithm. The VAD algorithm is GSAP(global speech absence probability) and the feedback cancellation algorithm is normalized LMS. The proposed algorithm applies different step-size between voice and non-voice using VAD, for high stability, fast convergence speed and low misalignment when correlated inputs, such as speech. The result of simulation with white noise mixed speech signal, the proposed algorithm shows high performance then traditional algorithm in terms of stability, convergence speed and misalignment.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.11
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• pp.963-970
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• 2016

This research deals with design and performance validation of eco-pedals that generate tactile pedal force to guide fuel saving driving behavior. For eco-pedal control logic, allowable fuel consumption at given driving speed is calculated based on pre-defined "allowable acceleration", and if the actual fuel consumption exceeds the allowable fuel consumption, then pedal force is activated. Pedal force should be recognizable to driver while not causing unpleasantness, and should not interfere with normal operation of pedal. Reaction forces that increase pedal stiffness abruptly, such as step and ramp shape, turn out to be not suitable due to pedal overshoot after release of reaction force. With this regards, vibration type reaction force is adopted, and its optimal frequency, magnitude and duration is determined through subjective evaluation with consideration to effect to fuel efficiency. Though highway and city driving test, it is demonstrated that fuel efficiency increase of 13% for highway and 15% for city is achieved.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.364-370
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• 2014

In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.1
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• pp.42-47
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• 2010

Many contests by micro mouse was celebrated of which maze search algorithms performance are compared. That is used in various forms based on left(right) weight method, euclidean algorithm method, hill climbing method. However we feel uncomfortable to test algorithms performance through direct development of programs or hardwares as no software platform to test in maze search algorithms. In this research we develop of a platform for maze search algorithms that is easily to produce various forms of maze that are hard to be realized by hardware, to apply algorithms, and evaluate the seek time, operation count, steps and performance. The platform is consist of main layer, interface layer, user layer which has merit to apply and replace easily algorithms. We verified that the maze search algorithm can be applied even in the development and experiment of algorithm by evaluating and analyzing its performance through the experiment of platform.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.12
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• pp.1555-1569
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• 2000

Numerical simulation of fluid flow with moving free surface has been carried out. For the free surface flow, a VOF(Volume of Fluid)-based algorithm utilizing a fixed grid system has been investigated. In order to reduce numerical smearing at the free surface represented on a fixed grid system, a new free surface tracking algorithm based on the donor-acceptor scheme has been presented. Novel features of the proposed algorithm are characterized as two numerical tools; the orientation vector to represent the free surface orientation in each cell and the baby-cell to determine the fluid volume flux at each cell boundary. The proposed algorithm can be easily implemented in any irregular non-uniform grid systems that are usual in finite element method (FEM). Moreover, the proposed algorithm can be extended and applied to the 3-D free surface flow problem without additional efforts. For computation of unsteady incompressible flow, a finite element approximation based on the explicit fractional step method has been adopted. In addition, the SUPG(streamline upwind/Petrov-Galerkin) method has been implemented to deal with convection dominated flows. Combination of the proposed free surface tracking scheme and explicit fractional step formulation resulted in an efficient solution algorithm. Validity of the present solution algorithm was demonstrated from its application to the broken dam and the solitary wave propagation problems.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.236.2-236.2
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• 2014

세계 반도체 시장은 컴퓨터 기능이 더해진 모바일 기기의 수요가 증가함에 따라 메모리반도체의 시장규모가 최근 빠른 속도로 증가했다. 특히 모바일 기기에서 저장장치 역할을 하는 비휘발성 반도체인 NAND Flash Memory는 스마트폰 및 태블릿PC 등 휴대용 기기의 수요 증가, SSD (Solid State Drive)를 탑재한 PC의 수요 확대, 서버용 SSD시장의 활성화 등으로 연평균 18.9%의 성장을 보이고 있다. 이러한 경제적인 배경 속에서 NAND Flash 미세공정 기술의 마지막 단계로 여겨지는 1Xnm 공정이 개발되었다. 그러나 1Xnm Flash Memory의 생산은 새로운 제조설비 구축과 차세대 공정 기술의 적용으로 제조비용이 상승하는 단점이 있다. 이에 따라 제조공정기술을 미세화하지 않고 기존의 수평적 셀구조에서 수직적 셀구조로 설계 구조를 다양화하는 기술이 대두되고 있는데 이 중 Flash Memory의 대용량화와 수명 향상을 동시에 추구할 수 있는 3D NAND 기술이 주목을 받게 되면서 공정기술의 변화도 함께 대두되고 있다. 3D NAND 기술은 기존라인에서 전환하는데 드는 비용이 크지 않으며, 노광장비의 중요도가 축소되는 반면, 증착(Chemical Vapor Deposition) 및 식각공정(Etching)의 기술적 난이도와 스텝수가 증가한다. 이 중 V-NAND 3D 기술에서 사용하는 박막증착 공정의 경우 산화막과 질화막을 번갈아 증착하여 30layer 이상을 하나의 챔버 내에서 연속으로 증착한다. 다층막 증착 공정이 비정상적으로 진행되었을 경우, V-NAND Flash Memory를 제조하기 위한 후속공정에 영향을 미쳐 웨이퍼를 폐기해야 하는 손실을 초래할 수 있다. 본 연구에서는 V-NAND 다층막 증착공정 중에 다층막의 두께를 가상 계측하는 알고리즘을 개발하고자 하였다. 증착공정이 진행될수록 박막의 두께는 증가하여 커패시터 관점에서 변화가 생겨 RF 신호의 진폭과 위상의 변화가 생긴다는 점을 착안하여 증착 공정 중 PECVD 장비 RF matcher와 heater에서 RF 신호의 진폭과 위상을 실시간으로 측정하여 데이터를 수집하고, 박막의 두께와의 상관성을 분석하였다. 이 연구 결과를 토대로 V-NAND Flash memory 제조 품질향상 및 웨이퍼 손실 최소화를 실현하여 제조 시스템을 효율적으로 운영할 수 있는 효과를 기대할 수 있다.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2196-2203
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• 1999

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.