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http://dx.doi.org/10.12673/jant.2014.18.4.364

A New Manufacturing Technology and Characteristics of Trench Gate MOSFET  

Baek, Jong-Mu (Department of Electronic Communication Engineering, Daewon University College)
Cho, Moon-Taek (Department of Electrical & Electronic Engineering, Daewon University College)
Na, Seung-Kwon (Department of Biomedical Engineering, Korea Polytechnic College Wonju Campus)
Publication Information
Journal of Advanced Navigation Technology / v.18, no.4, 2014 , pp. 364-370 More about this Journal
Abstract
In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.
Keywords
MOSFET; Trench; Self-align; DMOSFET; Mask layers;
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  • Reference
1 B. J. Baliga, Power semiconductor Devices, Boston, MA: PWS Publishing Company, 2012.
2 S. Chae, K. Park, S. Han, J. Ha and J. Park, "Plasma induced charging damage on thin gate oxide," IEEE Transactions on. Electronic Devices, Vol. ST-P19, pp. 497-500, Feb., 1999.
3 K. Shenai, P. A .Piacente, R. Saia, W. Hennessy, C. C. Korman, and B. J. Baliga, "A novel high-frequency power FET structure fabricated using LPCVD WSi2 gate and LPCVD W source contact technology," IEDM Technical Digest, pp. 804-808, Dec., 1985.
4 D. Ueda, H, Takagi and G. Kano, "An ultra-low on resistance power MOSFET fabricated by using a fully self aligned process," IEEE Transactions on Electronic Devices, Vol. ED-34, No. 4, pp. 926-930, Apr., 1987.
5 M. Sato and Y. Arita, "Etched Shape Control of Single-Crystal Silicon in Reactive Ion Etching Using Chlorine," Journal of The Electrochemical Society, Vol. 134, pp. 2856, 1987.   DOI
6 F.Fong, D. Pitzer and R. J.Zeman, "Power DMOS for high frequency and switching application", IEEE Transactions on. Electronic Devices, Vol. ED-27, No. 2, pp.322-330, Feb., 1980.
7 G. Chen, S. Sapp, N.Wylie and C. Hu, "A novel contact process for power MOSFET's," IEEE Electronic Devices Letters, Vol. EDL-7, No.12, pp.672-673, Dec., 1986.
8 B. J. Baliga, "A power junction gate field-effect transistor structure with high blocking gain," IEEE Transactions on. Electronic Devices, Vol. ED-27, pp.368-373, Feb. 1980.
9 J. D. Mein, et al.,"A high voltage MOS switch," IEEE F. Solid-State Circuits, Vol. SC-10, pp.136-146, June 1975.
10 S. Chae, K. Park, S. Han, J. Ha and J. Park,"Plasma induced charging damage on thin gate oxide," IEEE Transactions on Electronic Devices, Vol. ST-P19, pp. 497-500, Feb. 1999.