• Journal of the Society of Naval Architects of Korea
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• v.34 no.2
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• pp.27-38
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• 1997

This paper is concerned with the calculation of the wave resistance for SWATH ships based on a low order Rankine source panel method. Two types of free surface boundary conditions, Dawson type (double model approximation) and Kelvin type (free stream approximation) are used. For the free surface boundary calculation, an analytic differentiation is employed instead of implementing a finite difference scheme. Then, the radiation condition is satisfied by, so called, the panel shift method. The numerical results using the above two methods are compared with those using the thin ship/modified slender body approximation and also with the experimental results. The SWATH models considered are a single strut SWATH and a twin strut SWATH together with the variations of two demihull separation distance. In order to prove the validity of the program developed, the numerical calculations for a Wigley mono hull and Wigley twin hulls are compared with the available experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.364-370
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• 2014

In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.169-179
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• 1999

In this paper, a GaAs MESFET single-ended resistive mixer with high linearity and isolation is designed. The bias voltage of this mixer is applied only gate of GaAs MESFET to use the channel resistance. The LO is applied the gate and the RF is applied the drain through 7-pole hairpin bandpass filter to obtain the proper isolation thru LO-RF. The IF is extracted from the source with short circuit and lowpass filter. Using extracted equivalent circuits for LO and RF, conversion loss is calculated and compared with result of harmonic balance analysis. Measured conversion loss of this S-band down converter mixer is 8.2~10.5dB by considering the measured 3.0~3.4dB RF 7-pole hairpin bandpass filter loss and IP3in is 26.5dBm at Vg=-0.85~-1.0V in distortion performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.46-54
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• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.49-54
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• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.7
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• pp.1044-1052
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• 1999

A 2-stage 1 watt MMIC(Monolithic Microwave Integrated Circuits) HPA(High Power Amplifiers) at 20 GHz band has been designed and fabricated. The $0.15\mu\textrm{m}$ with the width of $400\mu\textrm{m}$for single device pHEMT technology was used for the fabrication of this MMIC HPA. Due to the series feedback technique from source to ground, bias circuits and stabilization circuits on the main microstrip line, the stability factors(Ks) are more than one at full frequency. The independent operation for each stage and excellent S11, S22 less than -20 dB have been obtained by using lange couplers. For beginning the easy design, linear S-parameters have been extracted from the nonlinear equivalent circuit in foundry library, and equivalent circuits of devices at in/output ports were calculated from this S-parameters. The measured performances, which are in well agreement with the predicted ones, showed the MMIC HPA in this paper has the minimum 15 dB of linear gain, -20 dB of reflection coefficients and 31 dBm of output power over 17~25 GHz.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.95-99
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• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.23 no.3
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• pp.1-1
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• 1987

The accurate prediction of the ship wave resistance is very important to design ships which operate satisfactorily in a wave environment. Thus, work should continue on development and validation of methods to compute ship wave patterns and wave resistance. Research efforts to improve the prediction of ship waves and wavemaking resistance are categorized in two major areas. First is the development of higher-order theories to take account of the nonlinear effect of the free surface condition and improved analytical treatment of the body boundary condition. Second is the development of direct numerical methods aimed at solving body and free-surface boundary conditions as accurately as possible. A new formulation of the slender body theory for a ship with constant speed is developed by Maruo. It is quite different from the existing slender ship theory by Vossers, Maruo and Tuck. It may be regarded as a substitute for the Neumann-Kelvin approximation. In present work, the method of asymptotic expansion of the Kelvin source is applied to obtain a new wave resistance formulation in fluid of finite depth. It takes a simple form than existing theory.