• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.886-889
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• 2006

수치연산 보조프로세서로도 알려져 있는 부동 소수점 연산장치(FPU)는 컴퓨터가 사용하는 기본 마이크로프로세서보다 더 빠르게 숫자를 다를 수 있는 특별한 회로 설계 또는 마이크로프로세서를 말한다. FPU는 전적으로 대형 수학적 연산에만 초점을 맞춘 특별한 명령 셋을 가지고 있어서 그렇게 빠르게 계산을 수행할 수 있는 것이다. FPU는 오늘날의 거의 모든 PC에 장착되고 있지만, 실은 그것은 그래픽 이미지 처리나 표현 등과 같은 특별할 일을 수행할 때에 필요하다. 초창기 컴퓨터 회사들은 각기 다른 연산방식을 사용했다. 이에 따라 연산결과가 컴퓨터마다 다른 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이 표준안은 IEEE Standard 754 이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점 표준안 중 32-bit 단일 정밀도 부동 소수점 가산기를 VHDL로 구현하여 FPGA칩으로 다운하고 PCI 인터페이스를 통해 Visual C++로 데이터의 입출력을 검증하였다.

• Applied Biological Chemistry
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• v.33 no.1
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• pp.52-61
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• 1990

Fish protein was acylated with acetic anhydride(AA), succinic anhydride(SA) and maleic anhydride(MA) in order to improve the functional properties of the protein. The surface hydrophobicity and functional properties of protein were measured to study the relationship between them. It was found that the extented acylation of nucleophilic groups such as amino and sulfhydryl groups of the amino acid residues of fish protein was higher than other groups when acylated with AA, and the degree of acylation was 89.5 % for amino groups and 72.2 % for sulfhydryl groups. The surface hydrophobicity of fish protein was decreased by succinylation and maleylation, whereas acetylation caused tittle change. The acylated fish protein concentrate(FPC) showed higher surface hydrophobicity than the acylated fish myofibrilla protein(FMP). Acylation with AA, SA and MA of fish protein resulted in a significant increase in protein solubility, emulsifier properties, foaming properties, water adsorption capacity and oil adsorption capacity. These properties of acylated FMP were more improved than those of acylated FPC. Decrease in protein hydrophobicity was highly correlated with increase in protein solubility, and emulsifier properties and foaming properties were largely dependent on the solubility as well as surface hydrophobicity. The water adsorption capacity of the protein was significantly affected by solubility. Surface hydrophobicity had greater influence on oil adsorption capacity, whereas it had tittle effect on water adsorption capacity.

• Communications of Mathematical Education
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• v.33 no.3
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• pp.255-273
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• 2019

In order to help students to understand the essence of prime concepts, this study looked at the history of prime concept development and analyzed how to introduce the concept of textbooks. In ancient Greece, primes were multiplicative atoms. At that time, the unit was not a number, but the development of decimal representations led to the integration of the unit into the number, which raised the issue of primality of 1. Based on the uniqueness of factorization into prime factor, 1 was excluded from the prime, and after that, the concept of prime of the atomic context and the irreducible concept of the divisor context are established. The history of the development of prime concepts clearly reveals that the fact that prime is the multiplicative atom is the essence of the concept. As a result of analyzing the textbooks, the textbook has problems of not introducing the concept essence by introducing the concept of prime into a shaped perspectives or using game, and the problem that the transition to analytic concept definition is radical after the introduction of the concept. Based on the results of the analysis, we have provided several pedagogical implications for helping to focus on a conceptual aspect of prime number.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.5B
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• pp.459-466
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• 2011

In this study, the resources investigations of small hydropower generation were carried out for the five proposed sites in northern Gyeong-buk area. They consisted of the discharge measurements, rating-curve, flow duration curves, electricity generation, and economic analysis, respectively. The basic data were suggested to select the optimal small hydropower sites in northern Gyeong-buk area. The sites for Yecheon Gun and Munsu Myeon as a result are the best proposed ones using economic analysis. We considered, however, that the finacial benefit for small hydropower development may be small under 500 kW facility. The optimal proposed site over 500 kW facility was suggested as Yeongyang Gun in this study.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.529-530
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• 2006

분산형 전원이 전력계통에 연계됨에 따라 역조류, 보호협조, 계통 동기화, 전기품질 문제 등 여러 가지 문제를 야기한다. 이에 따라 전력회사에서는 분산형 전원의 계통연계 기술 기준을 제시하고 해당 분산형 전원의 계통 연계에 대한 기술 검토를 수행한다. 본 논문에서는 동기발전기형 2500KVA 소수력발전기 2대의 배전계통 연계에 대한 기술적 검토를 수행하였으며 해당 분산형 전인이 동기발전기임을 고려하여 계통연계시 상시전압변동 및 보호방식에 대해 집중 분석하였다. 먼저 소수력발전기가 연계되는 지점에서의 기존 선로 및 전력설비의 여건과 소수력발전기의 출력용량 및 역률을 고려하여 연계 지점에서의 전압변동을 검토하여 적절한 연계방식을 제시한다. 그리고 시간대별 소수력발전기의 발전량과 해당 배전선로의 부하량을 고려하여 기 설치된 보호계전기에 의한 단독운전 검출 능력을 검토하고자 한다.

• Proceedings of the Korean Society of Fisheries Technology Conference
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• 2001.05a
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• pp.326-327
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• 2001

양어장 내에서 발생되는 어류의 배설물 중 단백질 성분은 미생물에 의해 분해되어 암모니아를 발생시키고 용존산소를 감소시키는 물질인 반면 소수기와 친수기를 함께 가지는 구조적 특성으로 인해 계면활성제 역할을 하여 별도의 계면활성제를 첨가하지 않아도 포말분리를 수행 할 수 있도록 해줌으로, 포말분리에 의한 양어장 순화수 중 어류에 유해한 성분의 처리수단으로써 많이 연구, 적용되어지고 있다. (중략)

• Journal of IKEEE
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• v.17 no.3
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• pp.346-351
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• 2013

Low-cost and low-power are important requirements in mobile systems. Thus, when a floating-point arithmetic unit is needed, 24-bit floating-point format can be more useful than 32-bit floating-point format. However, a 24-bit floating-point arithmetic unit can be risky because it usually has lower accuracy than a 32-bit floating-point arithmetic unit. Consecutive floating-point operations are performed in 3D graphic processors. In this case, the verification of the floating-point operation accuracy is important. Among 3D graphic arithmetic operations, the floating-point division is one of the most difficult operations to satisfy the accuracy of $10^{-5}$ which is the required accuracy in OpenGL ES 3.0. No 24-bit floating-point divider, whose accuracy is algebraically verified, has been reported. In this paper, a 24-bit floating-point divider is analyzed and it is algebraically verified that its accuracy satisfies the OpenGL requirement.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.