• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.79-84
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• 2007

In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.41-46
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• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1547-1550
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• 2002

MANET은 전형적인 무선 네트워킹과는 다른 새로운 무선 네트워킹 파라다임으로써 기존 유선 망의 하부 구조에 의존하지 않고 이동 호스트틀로만 구성된 네트워크이다. Ad Hoc망에서 통신을 하기 위해서는 출발지 노드에서 목적지 노드까지 데이터 전송을 위한 라우팅에 관한 문제이다. Ad Hoc망에서는 모든 단말기의 위치변화가 가능하기 때문에 경로설정에 어려움이 따른다. 노드간에 정보를 보내고자 할 때 노트가 인접한 상태가 아니면 정보를 직전 보낼 수 없고 여러 중간 노드들을 거쳐서 정보를 보내는 다중-홉 라우팅 방식을 사용해야 한다. 따라서 중간 노드들은 패킷 라우터의 역할을 해야하는데 무선 통신 자체가 좁은 대역폭과 한정된 채널을 가지고 전송 범위가 제한되는 문제가 있다. 또한 노트 자체의 이동성과 전력 소모 등으로 인한 이탈은 망 위상을 수시로 변화시키므로 노트간에 정보를 전송하는데 가장 종은 경로는 수시로 변경될 수 있으므로 많은 어려움이 따르게 된다. 본 논문에서는 이러한 문제의 해결방안으로 경로유지 과정에서 Ad Hoc망 내의 노드들은 이동성의 특성으로 인해 현재 사용되는 경로 보다 더 짧고 효율적인 경로가 발생하고 중간 노트가 이동 될 때 새로운 경로로 갱신하여 솔기없는 최적의 경로를 유지할 수 있는 방법을 제안한다. 제안 방법은 ZRP의 IERP에서 감청모드를 통하여 사공중인 경로보다 최적의 경로를 감지하여 새로운 경로로 갱신하는 방법과 중간 노드가 이동하여 경로가 깨진 경우 부분적으로 경로를 복구하는 방법을 제시하여 항상 최적화된 경로를 유지함으로써 Ad Hoc망의 위상변화에 대한 적응성을 높일 수 있도록 한다. SQL Server 2000 그리고 LSF를 이용하였다. 그리고 구현 환경과 구성요소에 대한 수행 화면을 보였다.ool)을 사용하더라도 단순 다중 쓰레드 모델보다 더 많은 수의 클라이언트를 수용할 수 있는 장점이 있다. 이러한 결과를 바탕으로 본 연구팀에서 수행중인 MoIM-Messge서버의 네트워크 모듈로 다중 쓰레드 소켓폴링 모델을 적용하였다.n rate compared with conventional face recognition algorithms. 아니라 실내에서도 발생하고 있었다. 정량한 8개 화합물 각각과 총 휘발성 유기화합물의 스피어만 상관계수는 벤젠을 제외하고는 모두 유의하였다. 이중 톨루엔과 크실렌은 총 휘발성 유기화합물과 좋은 상관성 (톨루엔 0.76, 크실렌, 0.87)을 나타내었다. 이 연구는 톨루엔과 크실렌이 총 휘발성 유기화합물의 좋은 지표를 사용될 있고, 톨루엔, 에틸벤젠, 크실렌 등 많은 휘발성 유기화합물의 발생원은 실외뿐 아니라 실내에도 있음을 나타내고 있다.>10)의 $[^{18}F]F_2$를 얻었다. 결론: $^{18}O(p,n)^{18}F$ 핵반응을 이용하여 친전자성 방사성동위원소 $[^{18}F]F_2$를 생산하였다. 표적 챔버는 알루미늄으로 제작하였으며 본 연구에서 연구된 $[^{18}F]F_2$가스는 친핵성 치환반응으로 방사성동위원소를 도입하기 어려운 다양한 방사성의 약품개발에 유용하게 이용될 수 있을 것이다.었으나 움직임 보정 후 영상을 이용하여 비교한 경우, 결합능 변화가 선조체 영역에서 국한되어 나타나며 그 유

• The KIPS Transactions:PartD
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• v.15D no.6
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• pp.755-766
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• 2008

Recently, NAND flash memory is becoming into the spotlight as a next-generation storage device because of its small size, fast speed, low power consumption, and etc. compared to the hard disk. However, due to the distinct characteristics such as erase-before-write architecture, asymmetric operation speed and unit, disk-based systems and applications may result in severe performance degradation when directly implementing them on NAND flash memory. Especially when a B-tree is implemented on NAND flash memory, intensive overwrite operations may be caused by record inserting, deleting, and reorganizing. These may result in severe performance degradation. Although ${\mu}$-tree has been proposed in order to overcome this problem, it suffers from frequent node split and rapid increment of its height. In this paper, we propose Log-Structured B-Tree(LSB-Tree) where the corresponding log node to a leaf node is allocated for update operation and then the modified data in the log node is stored at only one write operation. LSB-tree reduces additional write operations by deferring the change of parent nodes. Also, it reduces the write operation by switching a log node to a new leaf node when inserting the data sequentially by the key order. Finally, we show that LSB-tree yields a better performance on NAND flash memory by comparing it to ${\mu}$-tree through various experiments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1387-1394
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• 2004

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication systems. And it is well known about the fact that turbo code has better the BER performance as the number of decoding iterations increases in the AWGN channel environment. However, as the number of decoding iterations is increased under the several channel environments, any further iteration results in very little improvement, and it requires much delay, computation and power consumption in proportion to the number of decoding iterations. In this paper, it proposes the efficient iterative decoding stop criterion algorithm which can largely reduce the average number of decoding iterations of turbo code. Through simulations, it is verifying that the proposed algorithm can efficiently stop the iterative decoding by using the variance value of error probability for the soft output value, and can largely reduce the average number of decoding iterations without BER performance degradation. As a result of simulation, the average number of decoding iterations for the proposed algorithm is reduced by about 2.25% ~14.31％ and 3.79％ ~14.38% respectively compared to conventional schemes, and power consumption is saved in proportion to the number of decoding iterations.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.211-217
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• 2008

Recently, there are many efforts to support seamless mobility in 802.11 WLANs using IP Layer mobility protocols. The IP layer mobility protocols are the most efficient mechanism to guarantee the service session continuity when IP subnet is changed during handover. Even if the IP layer mobility protocols are quite efficient, the feature of the protocols that had been designed to consider only L3 layer makes it difficult to improve the performance of hand over more and more. Nowadays, to overcome this limitation of IP mobility protocols, many researchers have worked on the mobility protocols integration of different layers (e.g., L2 layer). In this paper, we propose the enhanced Proxy MIPv4 to minimize the latency of handover using MIH protocol in 802.11 WLANs. The proposed mechanism minimizes the latency of authentication by exchanging security keys between Access Routers during handover. Moreover, it also minimizes packet losses by Inter-AP Tunneling and data forwarding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.