• Annual Conference of KIPS
• /
• 2002.04b
• /
• pp.1615-1618
• /
• 2002

본 논문은 MAP(Maximum A Posteriori) 복호 알고리즘을 이용한 MAP Decoder의 설계에 관해 다룬다. 채널코딩기법은 채널을 통해서 디지털 정보를 전송할 때 신뢰성을 제공하기 위해서 사용되어 진다. 즉 수신단에서 수신된 정보의 오류를 검사하고 수정하기 위한 목적으로 송신단에서는 디지털 정보에 부가 정보를 첨가해서 전송하게 된다. 그래서 무선 이동 통신에서 성능이 우수한 채널코딩기법은 우수한 통신 품질을 위해서는 필수적이라고 할 수 있다. 최근에 Shannon의 한계에 매우 근접한 성능으로 많이 알려진 오류정정부호로 터보코드가 발표되었고 많은 연구가 진행되고 있다. 터보코드의 부호기로는 RSC(recursive systematic convolutional)코드가 사용되며 디코딩 알고리즘으로는 주로 MAP 복호 알고리즘을 사용한다. 본 논문에서 제안된 MAP 복호기는 하드웨어로 구현하기 위해서 변형된 LOG-MAP 복호 알고리즘을 이용하였고 터보디코더의 반복 복호에 이용할 수 있다.

• Annual Conference of KIPS
• /
• 2000.04a
• /
• pp.550-556
• /
• 2000

본 논문은 NP-complete문제중의 하나인 순서제약이 있는 병렬프로그램을 멀티프로세서 시스템 상에서 효율적으로 분배하기 위한 유전자 알고리즘 설계 방법을 제안한다. 순서제약 조건을 만족하게 하는 새로운 염색체 코딩방법 및 휴리스틱한 스케줄링 알고리즘으로 정법한 해를 생성하고 프로세서 효율성을 고려한 평가 함수(evaluation function)와 우수한 유전인자를 이용하여 교배하는 교배연산자 등을 제안하였다. 그리고 제안한 알고리즘을 실험한 결과, 순서제약이 있는 다양한 형태(topology)의 병렬프로그램 스케줄링 문제에 대해서 제안한 유전자 알고리즘의 타당성을 확인하였다.

• Annual Conference of KIPS
• /
• 2011.04a
• /
• pp.1317-1319
• /
• 2011

최근 이동통신 기술의 발전과 소형화된 무선 기기의 보급으로 위치 기반 서비스(Location-Based Service)의 이용이 보편화되고 있다. 위치 정보를 이용하기 위해서는 이동하고 있는 위치 정보를 일정한 주기마다 저장해야 하는데, 모바일 환경에서는 저장 공간의 제약 때문에 위치 정보를 짧은 주기로 저장한다면 정보의 정확도를 높일 수 있지만, 저장할 수 있는 정보의 양이 적어 장시간동안 위치 기반 서비스를 이용하는 데 불편함이 있을 수 있다. 이러한 이유 때문에 적은 저장 공간을 활용하면서 정보의 정확도를 높일 수 있는 압축 기법이 필요하다. 연속적인 위치 정보, 즉 좌표로 구성된 위치 정보들의 집합인 내비게이션 데이터를 압축하기에 적절한 공정 데이터 알고리즘들이 있는데, 이 알고리즘을 평가 및 비교 분석할 수 있는 성능 평가 도구인 NDCAAT(Navigation Data Compression Algorithm Assessment Tool)를 설계한다. NDCAAT는 GPS 및 네트워크 장비를 통해 위치 정보를 얻고, 이를 여러 압축 알고리즘을 적용하여 압축 알고리즘의 비교, 분석 및 성능평가를 하는 도구이다.

• Journal of Korean Society of Steel Construction
• /
• v.12 no.5 s.48
• /
• pp.569-579
• /
• 2000

An improved multi-level (IML) optimization algorithm using automatic differentiation (AD) of framed structures is proposed in this paper. For the efficiency of the proposed algorithm, multi-level optimization techniques using a decomposition method that separates both system-level and element-level optimizations, that utilizes and an artificial constraint deletion technique, are incorporated in the algorithm. And also to save the numerical efforts, an efficient reanalysis technique through approximated structural responses such as moments and frequencies with respect to intermediate variables is proposed in the paper. Sensitivity analysis of dynamic structural response is executed by AD that is a powerful technique for computing complex or implicit derivatives accurately and efficiently with minimal human effort. The efficiency and robustness of the IML algorithm, compared with a plain multi-level (PML) algorithm, is successfully demonstrated in the numerical examples.

• Journal of IKEEE
• /
• v.16 no.3
• /
• pp.274-282
• /
• 2012

In this paper, we propose the design of lighting control algorithm for intelligent LED lighting system. The proposed lighting control algorithm transmitted to MCU through a data bus the environmental information detected from respectively sensor node. The MCU control software was designed to determine the level maintained to depending on the set control method by comparing the results that calculated the dimming level using a signal value. Also, it was designed to be lighting by cross-performed periodically the rotation and reverse method by created fully symmetrical pattern using the control algorithm to LED lighting device. In this paper, the proposed lighting control algorithm improved the reliability of the data sent by designed the system that can be controlled lighting to stable, and it was maintained the event delivery ratio of 91%. Also, the lighting device was decreased the luminous intensity of 32%, the power consumption of 49%, and heat generation of 32%. As a result, it were could be improved the energy efficiency that the life-cycle of LED has been increased 50%.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.3_4
• /
• pp.149-159
• /
• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.42-49
• /
• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.2
• /
• pp.129-134
• /
• 2008

In this paper, we carry out the simulation for an optimal solution of one-dimensional nonlinear photonic crystal structure using Genetic algorithm, and show the proposed method to apply for photonic transistors. Unlike a conventional steepest descent method for an optimization, the proposed method based on Genetic Algorithm has advantages for finding out excellent solutions without any analytic forms, which can easily apply to other applications. Also, as several solutions around global minimum solution can be obtained, it is very good optimization tool to give us the patterns about the optimal structure of a photonic crystal transistor. To design an all-optical filter transistor, Neural network algorithm is firstly performed for an initial design and then Genetic Algorithm is finally used to get the optimal solution. From the simulation of one-dimensional photonic crystal transistor, 27dB of the switching On/Off ratio is obtained.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.11 no.9
• /
• pp.782-787
• /
• 2001

In this paper, we propose an growing and pruning algorithm to design the adaptive structure of modular wavelet neural network(MWNN) with F-projection and geometric growing criterion. Geometric growing criterion consists of estimated error criterion considering local error and angel criterion which attempts to assign wavelet function that is nearly orthogonal to all other existing wavelet functions. There criteria provide a methodology that a network designer can constructs wavelet neural network according to one s intention. The proposed growing algorithm grows the module and the size of modules. Also, the pruning algorithm eliminates unnecessary node of module or module from constructed MWNN to overcome the problem due to localized characteristics of wavelet neural network which is used to modules of MWNN. We apply the proposed constructing algorithm of the adaptive structure of MWNN to approximation problems of 1-D function and 2-D function, and evaluate the effectiveness of the proposed algorithm.

• Journal of Advanced Navigation Technology
• /
• v.22 no.4
• /
• pp.325-335
• /
• 2018

Limited access to state information in the design of a feedback controller has brought out a significant amount of research on the design of an output feedback controller. Despite its long endeavor to find an optimal one, it is still an open problem. Thus, we focus on the comparison of existing states of arts in the design of a static output feedback controller in terms of stability and complexity so as to find further research direction in this field. To this end, we present eight design methods in a unified presentation. We also provide the complete description of algorithms which can be applicable to any system configuration. Stability performance and complexity in terms of processing time are evaluated through numerical simulations. Simulation results show that the algebraic controller (AC) algorithm [20] has the smallest complexity while the scaling linear matrix inequality (SLMI) algorithm [18] seems to achieve the best stability in most cases with much higher complexity.