• Journal of the Korea Society of Computer and Information
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• v.18 no.6
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• pp.9-19
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• 2013

This paper deals with fuzzy $H_{\infty}$ filtering problem of discrete-time nonlinear Markovian jump systems with state and output time delays. The purpose is to design fuzzy $H_{\infty}$ filter such that the corresponding estimation error system with time delays and initial state uncertainties is stochastically stable and satisfies an $H_{\infty}$ performance level. A sufficient condition for the existence of fuzzy $H_{\infty}$ filter is given in terms of matrix inequalities. In order to relax conservatism, a stochastic mode dependent fuzzy Lyapunov function is employed. The Lyapunov function not only is dependent on the operation modes of system, but also includes the fuzzy membership functions. An illustrative example is finally given to show the applicability and effectiveness of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.25-32
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• 2007

In this paper, a new method for first order plus dead time(FOPDT) model identification is proposed, which can identity multiple points on a process step response in terms of classification of time response. The process input and output to the test are decomposed into the transient part and the steady-state part. The steady-state part express one FOPDT model and the transient part express variously FOPDT model using least square estimation method. The optimum parameter tuning algorithm for PID controller of the Smith Predictor is proposed through ITAE as performance index. The Simulation results show the validity and improvement of performance for various processes.

• Journal of the Earthquake Engineering Society of Korea
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• v.3 no.4
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• pp.47-60
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• 1999

The stability and efficiency of structural control systems depend on the accuracy of mathematical model of the system to be controlled. In this study, state equation models of a small scale test structure and an AMD(active mass damper) are obtained separately using OKID(observer/Kalman filter identification) which is a time domain system identification method. The test structure with each floor acceleration as outputs is identified for two inputs - the ground acceleration and the acceleration of the moving mass of AMD relative to the installation floor - individually and the two identified state equation models are integrated into one by model reduction method. The AMD is identified with the motor control signal as an input and the relative acceleration of the moving mass as an output, and it is shown that the identified model has large damping ratio and phase shift. The transfer functions and the time histories reconstructed from the identified models of the test model and the AMD match well with those measured from the experiment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.34-42
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• 1981

A 512-bit Task Programmable ROM has been designed and fabricated using PMOS technology. The content of the memory was written through the gate pattern during the fabrication process, and was checked by displaying the output of the chip on an oscilloscope with 512(32$\times$16) matrix points. The operation of the chip was surcessful with operating voltage from -6V to -l2V, The power consumption and propagation delay time have been measured to be 3mW and 13 $\mu$sec, respectively at -6 Volt. The power consunption increased to 27mW and propagation delay time decreased to 3$\mu$sec at -12V. The output of the chip was capable of driving the input of a TTL gate directly and retained a high impedence state when the chip solect function disabled the output.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.1-11
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• 2007

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.1 no.1
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• pp.63-70
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• 1995

퍼지논리제어기는 산업응용에 광범위하게 연구되고 있으며, 계속적으로 사용되고 있다. 그러나 퍼지집합의 조정을 통해 최적규칙을 구축하기 위하여, 시행착오에 의한 매우 능숙한 기술이 요구된다. 이 논문에서는 첫째로, 퍼지논리제어기와 기존의 PID 제어기로 구성된 하이브리드 퍼지제어기를 제안한다. 즉, 시스템의 제어 입력은 퍼지변수로서, 과도상태에서의 FLC출력과 정상상태에서의 PID 출력의 컨벡스(convex) 결합이다. 둘째로, 간략추론법과 개선된 컴플렉스방법을 이용한 강력한 자동동조알고리즘이 퍼지논리제어기의 성능을 자동적으로 개선하기 위하여 사용된다. 이방법은 오차변화율및 제어출력의 제한조건에 의하여, 언어제어규칙, 퍼지계수(scaling factor), PID계수, 하이브리드 퍼지논리제어기의 하중계수의 최적값을 자동적으로 추정한다. 시뮬레이션은 시간지연 플랜트및 하수처리시스템의 활성오니공정과 같은 비선형 플랜트에서 실행되고, 시스템의 성능은 평가지수 ITAE로 평가된다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.214-221
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• 2015

In this paper, we present robust estimation and detection algorithms for discrete-time switched linear systems whose output measurements are corrupted by noises. First, a mode estimation algorithm is proposed based on the minimum distance criterion. Then, state variables are also observed under the active mode estimate. Second, a detection algorithm is constructed to detect the mode switching of the switched system. With the boundedness of measurement noise, the proposed estimation algorithm returns the exact active mode and approximate state information of the switched system. In addition, the detection algorithm can detect the switching time within a pre-determined time interval after the actual switching occurred.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.520-534
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• 2003

In this paper, a performance evaluation model of the Fat-tree Network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch network. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are then evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.558-560
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• 2000

본 논문은 ATM(Abstract Timed Machine)에 대해서 기술한다. ATM 은 임무 위급 시스템과 같은 실시간 시스템을 명세, 분석 및 검증할 수 있는 정형 기법이다. ATM 은 모드(mode), 전이(transition), 포트(port)로 구성된다. 모드는 머신의 압축된 상태를 의미하고 전이는 모드와 모드 사이의 변화를 말한다. 포트는 ATM 들 사이의 상호작용을 위한 진입을 나타내기 위한 것이다. ATM 은 소프트웨어 순환 공학을 위해 디자인 되었다. ATM은 재/역공학적 측면에서 계산 이론과 더불어 기존의 실시간 시스템의 소스코드에 대한 디지안 및 환경 정보를 나타낸다. 본 논문은 병렬성, 병렬적으로 동작하는 엔터티들 사이의 제어 정보이 흐름, ATM 타입과 클래스로부터의 인스턴스, 비/동기적 이벤트, 포트와 이벤트 타입, 포트의 타입, 통신, 입/출력, 예외처리, 시간에 관한 요구사항, 다수를 대상으로 하는 통신 주기적 작업등과 같은 ATM의 여러 개념을 기술하고 이러한 속성들을 Producer-Buffer-Consumer 예제로 살펴본다.