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Performance Evaluation of a Fat-tree Network with Output-Buffered $a{\times}b$ Switches  

신태지 (울산대학교 전기전자 및 정보시스템공학부)
양명국 (울산대학교 전기전자 및 정보시스템공학부)
Abstract
In this paper, a performance evaluation model of the Fat-tree Network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch network. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are then evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed.
Keywords
Fat-tree Network; Buffer; Throughput; Delay; Analysis; Simulation;
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