• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• Electronics and Telecommunications Trends
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• v.30 no.6
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• pp.90-98
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• 2015

본 논문에서는 비동기식 회로기술의 최근 동향을 분석하기 위해 관련 분야의 가장 저명한 학회인 비동기식 회로 및 시스템 학회(International Symposium on Asynchronous Circuits and Systems: ASYNC)에 투고된 논문과 기존의 동향분석 자료를 비교 분석하여 제시하고, 관련 업체의 상용화 사례를 통한 비동기식 회로 기술전망을 제시한다. 조사된 논문은 2011년부터 2015년까지 투고된 총 90편의 논문을 각 기준에 따라 분류하고, 연도별, 국가별, 기관별 동향을 분석함으로 최근 관련 기술의 연구동향을 통계화하여 제시하였다. 분석 결과 지난 최근 3년 내 Low Power 분야가 주목할 만한 성장세를 보였고, 상용화 사례로는 Intel의 비동기식 설계를 통한 네트워크 칩, IBM의 Brain inspired processor인 TrueNorth 프로세서 등이 주목할 만하다.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.06a
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• pp.12-15
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• 2001

본 논문에서는 고효율 멀티미디어 프로세서 아키텍쳐에 대해 논의하였다. 제안한 멀티미디어 프로세서 아케텍쳐는 제안한 방법은 기존의 멀티미디어 프로세서의 단점들인 각종 텍스트, 사운드, 비디오 등의 미디어 들을 1개의 칩 속에서 처리할 수 있도록 하였으며, 또한 멀티미디어의 특성인 상호대화식 처리도 가능하게 하였다. 특히, 완전한 그래프에 기반을 둔 네트워크를 지향하므로 소프트웨어 없이 메모리 맵의 노드어드레싱을 가능하게 하였으며, 데이터 형태에 의존하는 완전한 재구성이 가능하며 동기/비동기를 갖는 시간 공유와 공간 공유 처리가 가능하다. 또한, 연속적임과 동적인 매체 데이터의 버스 충돌을 방지할 수 있으며 지역적임과 전반적인 공유 메모리 구조로부터의 버스 충돌도 방지할 수 있으며, 또한 가상현실과 흔합현실에도 적용할 수 있으리라 사료된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.42-56
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• 2002

It is possible but not efficient to model and simulate asynchronous microprocessors with the existing HDLs(HARDware Description Languages) such as VHDL or Verilog. The reason it that the description becomes too complex. and also the simulation time becomes too long to explore the design space. Therefore it is necessary to establish a methodology and develop a tool for modeling the handshake protocol of asynchronous microprocessors very easily and simulating it very fast. Under this objective an efficient CAD(Computer Aided Design) tool SLEDS(System Level Event-Driven Simulator) was developed which can evaluate performance of a processor through modeling with a simple description an simulating with event driven engine in the system level. The ultimate goal in the tool SLEDS is to fin the optimal conditions for a system to produce high performance by balancing the delay of each module in the system. Besides SLEDS aims at verifying the design through comparing the expected results with the actual ones by performing the defined behavior.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.1976-1979
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.