• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.338-343
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• 2006

This paper describes about the design concept and the architecture of an economic VPN system which can perform fast crypto operations with cheap cost. The essence of the proposed system architecture is consisting of the system with two companion chips dedicated to VPN: one chip is a multi-purpose network processor for security machine and the other is a crypto acceleration chip which encrypt and decrypt network packets in a high speed. This study also addresses about some realizations that is required for fast prototyping such as the porting of an operating system, the establishment of compiler tool chain, the implementation of device drivers and the design of IPSec security engine. Especially, the second chip supports the most time consuming block cipher algorithms including 3DES, AES, and SEED and its performance was evaluated.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.6
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• pp.959-964
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• 2001

An experimental investigation on the near-field electromagnetic loss of thin copper layers has been presented using microfabricated microwave transceivers for applications to multi-chip microsystems. Copper layers in the thickness range of 0.2$\mu$m∼200$\mu$m have been electroplated on the Pyrex glass substrates. Microwave transceivers have been fabricated using the 3.5mm$\times$3.5mm nickel microloop antennas, electroformed on the silicon substrates. Electromagnetic radiation loss of the copper layers placed between the microloop transceivers has been measured as 10dB∼40dB for the wave frequency range of 100MHz∼1GHz. The 0.2$\mu$m-thick copper layer provides a shield loss of 20dB at the frequencies higher than 300MHz, whereas showing a predominant decreases of shield loss to 10dB at lower frequencies. No substantial increase of the shield effectiveness has been found for the copper shield layers thicker that 2 $\mu$m.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.878-881
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• 2009

As for the technology developed for network security, there is little difference of design ability between the domestic and the foreign studies. Although the development of 2048 RSA processor has been undergone, the processing speed does not meet the requirement due to its long width. These days, an RSA processor architecture with higher speed comsuming less resource is necessary. As for the development of RNG (Random Number Generator), the technology trend is moving from PRNG (Pseudo Random Number Generator) to TRNG (True Random Number Generator), also requiring less area and high speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.17-23
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• 2003

In this study, microscale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was 1.0${\times}$0.5${\times}$0.5㎣. The materials (96% Al2O3) and shape (I-type) of the core were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. The copper (Cu) wire with 40${\mu}{\textrm}{m}$ diameter was used as the coils. High frequency characteristics of the inductance (L), quality-factor (Q), and capacitance (C) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 11 to 39 nH and quality factors of 28 to 50 over the frequency ranges of 250MHz to 1 GHz, and show results comparable to those measured for the inductors prepared by CoilCraf $t^{Tm}$ that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the L, Q, and C of the inductors developed well.l.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.43-48
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• 2004

Electromigration of Sn-3.5Ag-0.5Cu solder bumps was investigated with current densities of $3{\~}4{\times}10^4 A/cm^2$ at temperatures of $130{\~}160^{\circ}C$ using flip chip specimens which consisted of upper Si chip and lower Si substrate. Electromigration failure of the Sn-3.5Ag-0.5Cu solder bump occurred with complete consumption of Cu UBM and void formation at cathode side of the solder bump. The activation energies for electromigration of the Sn-3.5Ag-0.5Cu solder bump were measured as 0.61 eV at current density of $3{\times}10^4 A/cm^2$, 0.63 eV at $3.5{\times}10^4 A/cm^2$, and 0.77 eV at $4{\times}10^4 A/cm^2$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.9-15
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• 2008

Microstructure and contact resistance of the Au-Sn solder joints were characterized after flip-chip bonding of the Au/Sn bumps processed by successive electrodeposition of Au and Sn. Microstructure of the Au-Sn solder joints, formed by flip-chip bonding at $285^{\circ}C$ for 30 sec, was composed of the $Au_5Sn$+AuSn lamellar structure. The interlamellar spacing of the $Au_5Sn$+AuSn structure increased by reflowing at $310^{\circ}C$ for 3 min after flip-chip bonding. While the Au-Sn solder joints formed by flip-chip bonding at $285^{\circ}C$ for 30 sec exhibited an average contact resistance of 15.6 $m{\Omega}$/bump, the Au-Sn solder joints reflowed at $310^{\circ}C$ for 3 min after flip-chip bonding possessed an average contact resistance of 15.0 $m{\Omega}$/bump.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.86-93
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• 2010

A system-on-chip (SoC) includes more functions and requires rapidly increased data bandwidth as the development of semiconductor process technology and SoC design methodology. As a result, the data bandwidth of on-chip-networks in SoCs becomes a key factor of the system performance, and the research on the on-chip-network is performed actively. Either AXI or OCP is considered to a substitute of the AHB which has been the most popular on-chip-network. However, they have much increased number of signal wires, which make it difficult to design the interface logic and the network hardware. The compatibility of the protocols with other protocols is not so good. In this paper, we propose a new interface protocol for on-chip-networks to improve the problems mentioned above. The proposed protocol uses less number of signal wires than that of the AHB and considers the compatibility with other interface protocols such as the AXI. According the analysis results, the performance of the proposed protocol per wire is much better than that of the AXI although the absolute performance is slightly inferior.

• Journal of IKEEE
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• v.24 no.1
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• pp.46-51
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• 2020

With Wi-Fi and Bluetooth connectivity becoming more common in today's handheld mobile devices, single-chip multi-radio combo-modules, which integrate two or more heterogeneous wireless radios on a single chip, are becoming more and more popular. The key requirement for combo solutions is that the quality of the user experience (QoE) must not be compromised by degrading connectivity performance. Therefore, characterizing and understanding the behaviour of combo-module is of vital importance to ensure this requirement in various environments. In this paper, we investigate the impact of the use of combo-modules on the performance of mobile video streaming over a Wi-Fi network. Our study reveals that the use of combo-modules incurs considerable side effects on QoE for mobile video streaming applications when the Wi-Fi and Bluetooth operate at the same time in the 2.4GHz ISM band. We reveal that rate-based adaptive algorithms, including the most popular adaptive bitrate streaming MPEG-DASH, is more severely affected by this phenomenon than buffer-based adaptive algorithms.

• Journal of the Korea Convergence Society
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• v.9 no.3
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• pp.217-222
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• 2018

In this paper, a new micro polymer chip platform and protocol were developed for rare cell sample preparation. The proposed platform and protocol overcome the current limitation of the dilution method which is based on statistics and the FACS method which expensive and requires fluorescence staining. It allows collecting exact number of target cells simply and selectively because the cells are visually confirmed during the collecting process. The collected cells can be transported or spiked into a desired locations, such as a microchamber, without cell loss. This research may applicable not only to a rare cell sample preparation for Lab on a Chip cancer diagnosis, but also to a single/double/multiple cell sample preparation for a cell analysis field. To verify this platform and protocol, five human breast cancer cells (MCF-7) were collected and transported into a hemocytometer chamber.