• Journal of the Korean earth science society
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• v.24 no.8
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• pp.657-667
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• 2003

Deep-drilled core sampling and high-resolution seismic survey were carried out to identify a Holocene-late Pleistocene boundary in Gyeonggi Bay, western coast of Korea. Analysis of core sections revealed the existence of an oxidized and semi-consolidated sediment layer, Iying immediately below a Holocene horizon (Unit I) and being developed at the top of a late Pleistocene deposit (Unit II). The oxidized sedimentary layer (uppermost part of Unit II) is characterized by semi-consolidated, yellowish sediments showing signs of desiccation and alteration such as high N value, low water content, periglacial cryogenic structure, depletion of smectite, and high geochemical weathering index (Ba/Sr ratio). This feature, together with radiocarbon ages, suggests that the layer has formed as a result of prolonged subaerial exposure of Unit II sediments during the late Wisconsin sea-level lowstand, producing a regional unconformity. Such unconformitic-bounding surface corresponds to a prominent near-surface reflector (R), which is observed in seismic profiles obtained across the drilled-core sections in the study area. Consequently, the buried oxidized-sedimentary layer associated with the seismic reflector possibly plays a key horizon for the understanding of late Quaternary environmental changes as well as evidence of the emergence of the Yellow Sea shelf during the late Wisconsin sea-level lowstand.

• Economic and Environmental Geology
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• v.52 no.5
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• pp.381-393
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• 2019

Carbonate breccias occur sporadically in the Middle Cambrian Daegi Formation on the southern limb of the Baegunsan Syncline, Taebaeksan Basin. These carbonate breccias have been largely interpreted either as sedimentary breccias or as tectonic, fault-related breccias. Recent study, however, indicates that the majority of these breccias are a solution-collapse breccia which is causally linked to the paleokarstification. Extensive karstification is attributed to prolonged subaerial exposure of the carbonate platform. The exposed surface is a record of interruption in sedimentation on the carbonate platform. In the stratigraphic record, such karst-related post-depositional features are recognized as meteoric diagenetic features, paleosols, and solution-collapse breccias. Solution-collapse breccias are particularly well preserved and most profound in the carbonate rocks below the major unconformities, which also are evidence of prolonged subaerial exposure. The Middle Cambrian Daegi Formation provides an example of solution-collapse breccias. The formation and preservation of the solution-collapse breccias imply that a stratigraphic discontinuity surface (unconformity) can be designated within the Daegi Formation.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.66-70
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• 2016

This paper presents an 24 GHz I/Q LO generator for a heartbeat measurement radar system. In order to improve the mismatch performance between I and Q LO signals against process variation, a 24 GHz I/Q LO generator employing a low-pass phase shifter and a high-pass phase shifter composed of inductors and capacitors is proposed. The proposed 24 GHz I/Q LO generator consists of an LO buffer, a low-pass phase shifter and a high-pass phase shifter. It was designed using a 65 nm CMOS technology and draws 8 mA from a 1 V supply voltage. The proposed 24 GHz I/Q LO generator shows a gain of 7.5 dB, a noise figure of 2.3 dB, 0.1 dB gain mismatch and $4.3^{\circ}$ phase mismatch between I and Q-path against process and temperature variations for the operating frequencies from 24.05 GHz to 24.25 GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.2 no.2
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• pp.138-150
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• 1997

The late Quaternary stratigraphy of the tidal deposits in the Hampyung Bay, southwestern coast of Korea comprises 1) Unit III (nonmarine fluvial coarse-grained sediments), 2) Unit II (late Pleistocene tidal deposits), and 3) Unit I (late Holocene fine-grained tidal deposits) in ascending order. The basements of the Hampyung Bay is composed of granitic rocks and basic dyke rocks. These three units are of unconformally bounded sedimentary sequences. The sequence boundary between Unit I and Unit II, in particular, seems to be significant suggesting erosional surface and exposed to the air under the cold climate during the LGM. The uppermost stratigraphic sequence (Unit I) is a common tidal deposit formed under the transgression to highstand sea-level during the middle to late Holocene.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.94-99
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• 2010

This paper presents a charge pump architecture for correcting the current mismatch due to the PVT variation. In general, the current mismatch of the charge pump should be minimized to improve the phase noise and spur performance of the PLL. In order to correct the current mismatch of the charge pump, the current difference is detected by the replica charge pump and fed back into the main charge pump. This scheme is very simple and guarantees the high accuracy compared with the prior works. Also, it shows a good dynamic performance because the mismatch is corrected continuously. It is implemented in 0.13um CMOS process and the die area is $100{\mu}m\;{\times}\;160{\mu}m$. The voltage swing is from 0.2V to 1V at supply voltage of 1.2V. The charging and discharging currents are $100{\mu}A$, respectively and the current mismatch due to the PVT variation is less than 1%.

• Journal of the Korean earth science society
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• v.40 no.2
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• pp.163-176
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• 2019

The Potosinian geological basement in central Mexico is comprised of the Upper Paleozoic metamorphic rocks, which crop out on the Sierra de Catorce nucleus located in the northeastern part of the state. The sedimentary sequence that covers unconformably the Paelozoic basement is represented by an Upper Triassic marine sedimentary sequence, correlating to the Zacatecas Formation and the Upper Triassic continental Huizachal Formation red beds, which in turn are covered either by La Joja Formation Jurassic red beds or by Upper Jurassic marine sediments. This sequence is overlain by the conformable Cretaceous calcareous marine sedimentary rocks in all the state of San Luis Potosi. The Cenozoic sequence unconformably covers some of the aforementioned rocks and is represented by undifferentiated volcanic rocks as well as by marine clastic rocks. The existing intrusive igneous rocks are felsic to intermediate composition, and they intrude the metamorphic basement and sedimentary rocks. Conglomerates with evaporitic sediments were deposited during the Pleistocene. The Quaternary sequence includes basalt flows, piedmont deposits, alluvium, and occasionally evaporites and caliche layers. In the state of San Luis Potosi, a great diversity of mineral deposit types is known as both metallic and nonmetallic. The host rocks of these deposits vary from one another including formations that represent from Paleozoic up to Tertiary. The mineralization age corresponds approximately to Tertiary (75%), and is mainly epigenetic. Conclusively, the data on geology and mineralization in San Luis Potosi, Mexico are helpful to predict a hidden ore body and select promising mineralized zone(s) when the domestic company makes inroads in the mining sector of Mexico.

• Agrochemical news magazine
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• v.25 no.8 s.201
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• pp.6-9
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• 2004

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.10-12
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• 2002

본 논문에서는 TEM Cell 의 최적 설계방법을 제안한다. 임피던스 부정합을 최소화 시키기 위해 Cell 내부의 특성 임피던스를 $50{\Omega}$으로 유지하며, 동시에 중심 도체판(Septum)의 길이와 도체판 날개(winglet)의 각을 변화 시킴으로써 내부 전자파의 균일도(Uniformity)를 최대로 하는 TEM Cell의 최적설계 방법을 제안하며 (1+1)ES를 적용하여 시험영역을 최대로 하는 최적 설계 변수들을 제시한다.