• Proceedings of the KAIS Fall Conference
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• 2010.05b
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• pp.981-984
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• 2010

생산성 증가 및 비용 절감을 위해 반도체 공정 기술을 단순화 시키는 것이 필요하다. WBL(Wafer Backside Lamination) 기술을 이용해 필름(film) 형태로 얇은 다이접착제를 웨이퍼(wafer)에 접착하여 반도체 칩과 PCB를 붙이는 방법과 직접 PCB에 다이접착제를 붙이는 방법을 사용하면 획기적으로 공정을 단순화 시킬 수 있다. 하지만 Lamination 기법은 고온을 이용하여 모듈화된 PCB에 접착하므로 전도와 복사에 의해 주변 접착제 필름이 녹아 버리는 문제점이 발생한다. 본 연구에서는 고온으로 인한 필름 융해 현상을 방지하기 위하여 배크라이트를 설치하였으며 CFD 해석을 통해 PCB와 반도체 칩을 접착시킬 때 열이 PCB에 미치는 영향을 살펴보았다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.1364-1369
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• 2015

As the wire bonding process has been converted into BUMP process due to the high density integration of semiconductor chip, the telecommunication line connecting to semiconductor chip and external devices have become finer. As a result, a more precise work is necessary. However, it is difficult to control quantity given the nature of high viscosity of PSPI and the yield rate continues to decline due to the inflow of bubble. Therefore, this paper developed the D&P(degassing and pumping) system to remove and supply gas that is generated from coating the high viscosity photosensitive polyimide(PSPI) in the semiconductor BUMP process.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• Transactions of Materials Processing
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• v.31 no.4
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• pp.179-185
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• 2022

The influence of post-roll bonding heat treatment conditions such as temperature and time on the variation in the diffusion layer, generated at the bonding interface and the subsequent mechanical properties of the roll-bonded Ti grade 1/Al1050/Ti grade 1 sheets, was systematically investigated. The intermetallic compound (IMC) phase generated by post heat treatment conditions adopted in this study was obviously indexed as monolithic TiAl₃. Whereas the thickness of IMC layer generated by annealing at 500 ℃ was approximately 100 nm scale, it drastically increased above 1.5 ㎛ when annealed at 600 ℃. Uniaxial tensile and peel tests were then performed to compare mechanical properties. As a result, the bonding strength drastically increased above 7.9 N/mm by annealing at 600 ℃, which implies that proper annealing condition was a prerequisite, to improving interface bonding strength as well as global elongation properties for Ti/Al/Ti 3-ply sheet.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.4
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• pp.351-357
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• 2013

In flip chip packaging, underfill process is used to fill epoxy bonder into the gap between a chip and a substrate in order to improve the reliability of electronic devices. Underfill process by capillary motion can give rise to unwanted air void formations since the arrangement of solder bumps affects the interfacial dynamics of flow meniscus. In this paper, the unsteady flows in the capillary underfill process are visualized and then the racing effect and merging of the meniscus are investigated according to the arrangement of solder bumps. The result is shown that at higher bump density, the fluid flow perpendicular to the main direction of flow becomes stronger so that more air voids are formed. This phenomenon is more conspicuous at a staggered bump array than at a rectangular bump array.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.53-58
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• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.61-68
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• 2023

In this study, Sn-3.5Ag-15.0Fe composite solder was manufactured and applied to TLP bonding to change the entire joint into a Sn-Fe IMC(intermetallic compound), thereby applying it as a high-temperature solder. The FeSn₂ IMC formed during the bonding process has a high melting point of 513℃, so it can be stably applied to power modules for power semiconductors where the temperature rises up to 280℃ during use. As a result of applying ENIG surface treatment to both the chip and substrate, a multi-layer IMC structure of Ni₃Sn₄/FeSn₂/Ni₃Sn₄ was formed at the joint. During the shear test, the fracture path showed that cracks developed at the Ni₃Sn₄/FeSn₂ interface and then propagated into FeSn₂. After 2hours of the TLP joining process, a shear strength of over 30 MPa was obtained, and in particular, there was no decrease in strength at all even in a shear test at 200℃. The results of this study can be expected to lead to materials and processes that can be applied to power modules for electric vehicles, which are being actively researched recently.

• Journal of Adhesion and Interface
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• v.25 no.2
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• pp.63-68
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• 2024

In this study, the contamination of gold(Au) wire according to the types of rinse applied for surface treatment in the wire bonding process is investigated and confirmed. For the surface treatment, rinses containing silicon(Si) or those based on organic materials are mainly employed. To identify their effects, surface treatment is conducted on Au wire using two types of rinse at a 1.0 wt% concentration, referred to as Si-including and Oil-based rinse-coated Au wire. Subsequently, a simulation experiment is performed to verify the reactivity of dust containing Si components that could occur in the semiconductor process. Through optical microscopy (OM) and scanning electron microscopy(SEM) analysis, it is observed that a larger amount of dust is adsorbed on the surface of Si-including rinse-coated Au wire compared with the Oil-based rinse-coated Au wire. This is attributed that the rinse containing Si components is relatively polar, causing polar interactions with dust, which also has polarity. Therefore, it is expected that using a rinse without Si components can reduce contamination caused by dust, thereby decreasing the defect rate in the practical wire bonding process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.129-129
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• 2017

열전재료는 열에너지를 전기에너지로 또는 전기에너지를 열에너지로 직접 변환하는데 가장 널리 사용되는 재료이다. $Bi_2Te_3$계 열전 재료는 400K 이하의 비교적 저온 영역에서 높은 성능지수(Dimensionless Figure of merit, ZT($={\alpha}2{\sigma}T/{\kappa}$, ${\alpha}$: 제백계수, ${\sigma}$: 전기전도도, T: 절대온도, ${\kappa}$: 열전도도))를 나타내는 열전재료이며 자동차 시트나 정수기 등에 응용되고 있다. 열전모듈은 제조시 수십 개에서 수백 개 이상의 n형 및 p형 열전소자를 알루미나($Al_2O_3$)와 같은 세라믹 기판(substrate) 상에 접합된 동 전극 위에 전기적으로 서로 직렬로 접합시켜 제조한다. 기존의 열전모듈의 제조방법에는 동 전극 위에 위에 Sn합금 분말과 플럭스(flux)의 혼합물인 솔더페이스트를 스크린 인쇄법을 사용하여 동 전극에 도포한 다음, 그 위에 열전소자를 얹고 약 520K의 열풍을 가하여 솔더를 용융시켜 열전소자와 동 전극을 접합시킨다. 스크린 인쇄법에서는 인쇄 압력이 일정하지 않으면, 솔더페이스트 층의 두께가 균일하지 않게 되어 열전소자 접합부의 불량을 유발시킨다. 그러나 열모듈은 단 하나의 접합 불량이 모듈 전체의 열전변환성능에 심각한 영향을 줄 수 있기 때문에 본 연구에서는 이러한 문제점을 해결하기 위해, 솔더페이스트를 도포하지 않고 열전소자를 직접 동 전극과 접합할 수 있는 방법을 고안하였다. 무전해도금을 이용한 니켈층을 형성시킨 $Bi_2Te_3$계 열전소자 표면에 약 $50{\mu}m$의 주석도금층을 전기도금법을 구사하여 형성시켰다. 그 후, wire cutting을 통하여 $3mm{\times}3mm{\times}3mm$의 크기로 절단한 주석도금된 열전소자를 동 전극에 얹고 1.1KPa의 압력을 가하면서 523K의 핫플레이트 위에서 3분간 방치하여 직접(direct) 열압착 접합을 실시하였다. 접합부의 단면을 SEM을 이용하여 관찰한 결과, 동 전극과 열전소자 사이의 계면에 용융 후 응고된 주석층이 결함없이 균일하게 형성된 양호한 접합부를 관찰할 수 있었다. 따라서, 솔더페이스트를 이용하지 않고, 열전소자 표면에 주석도금을 실시한 후, 동 전극과 직접 열압착 본딩을 실시하는 방법은 균일한 접합계면을 얻을 수 있는 새로운 공정으로 기대된다.