• Title/Summary/Keyword: 본딩 공정

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Development of Cu CMP process for Cu-to-Cu wafer stacking (Cu-to-Cu 웨이퍼 적층을 위한 Cu CMP 특성 분석)

  • Song, Inhyeop;Lee, Minjae;Kim, Sungdong;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.81-85
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    • 2013
  • Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

PCB 표면처리 및 공정 약품 기술 동향

  • Kim, Ik-Beom
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2014.11a
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    • pp.77-77
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    • 2014
  • 솔더링과 와이어본딩이 가능한 ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold) 를 중심으로 미세회로 기판에 적용할 수 있는 표면처리 및 공정 약품을 소개하고자 한다.

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Flip Chip Process on CNT-Ag Composite Pads for Stretchable Electronic Packaging (신축성 전자패키징을 위한 CNT-Ag 복합패드에서의 플립칩 공정)

  • Choi, Jung Yeol;Oh, Tae Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.17-23
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    • 2013
  • As a basic research to develop stretchable electronic packaging technology, CNT-Ag composite pads were formed on top of Cu/Sn chip bumps and flip-chip bonded using anisotropic conductive adhesive. Average contact resistances of the flip-chip joints were measured with respect to bonding pressure and presence of the CNT-Ag composite pads. When Cu/Sn chip bumps with CNT-Ag composite pads were flip-chip bonded to substrate Cu pads at 25MPa or 50 MPa, contact resistance was too high to measure. The specimen processed by flip-chip bonding the Cu/Sn chip bumps with CNT-Ag composite pads to the substrate Cu pads exhibited an average contact resistance of $213m{\Omega}$. On the other hand, the flip-chip specimens processed by bonding Cu/Sn chip bumps without CNT-Ag composite pads to substrate Cu pads at 25MPa, 50MPa, and 100MPa exhibited average contact resistances of $370m{\Omega}$, $372m{\Omega}$, and $112m{\Omega}$, respectively.

Study of micro flip-chip process using ABL bumps (ABL 범프를 이용한 마이크로 플립 칩 공정 연구)

  • Ma, Junsung;Kim, Sungdong;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.2
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    • pp.37-41
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    • 2014
  • One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

Development of Bonding Dispenser and Press Machine to Regenerate Retainer Ring for Semiconductor CMP Process (반도체 CMP 공정용 리테이너 링 재생을 위한 본딩 디스펜서 및 프레스 머신 개발)

  • Hyoung-Keun Park
    • The Journal of the Korea institute of electronic communication sciences
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    • v.19 no.3
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    • pp.507-514
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    • 2024
  • In the semiconductor manufacturing line, continuous efforts are being made to reduce the cost of products produced, and the demand for this is accelerating in the chemical mechanical polishing(CMP) process, and a representative example of these cost reduction items is the 5-Zone Ring. After about 150 hours of use in the CMP process, the thickness of the ring decreases to less than 1 mm and must be replaced with a new product. Therefore, in this study, bonding dispensers and press machines with a dispensing amount error of 10g±0.8% or less and a pressure uniformity of ±1.8% or less were developed to reduce semiconductor manufacturing costs by repeatedly regenerating worn parts of the retainer ring, and to minimize environmental pollution caused by industrial waste treatment.

Development of Uniform Press for Wafer Bonder (웨이퍼 본딩 장비용 Uniform Press 개발)

  • Lee, Chang-Woo;Ha, Tae-Ho;Lee, Jae-Hak;Kim, Seung-Man;Kim, Yong-Jin;Kim, Dong-Hoon
    • Transactions of the KSME C: Technology and Education
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    • v.3 no.4
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    • pp.265-271
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    • 2015
  • The bonding process should be achieved in vacuum environment to avoid air bubble. In this study, we studied about pressure uniformity that became an issue in thermo compression bonding usually. Uniform press is realized by the method that use air spring and metal form spring. The concept of uniform press using air spring is removed except pressing direction in the press processing so angle between the vector of pressure surface and the pressure axis is parallel automatically. Air spring compensate the errors of machining and assembly. Metal form compensate the thermal deformation and flatness error.

LED Die Bonder Inspection System Using Integrated Machine Visions (Integrated Machine Vision을 이용한 LED Die Bonder 검사시스템)

  • Cho, Yong-Kyu;Ha, Seok-Jae;Kim, Jong-Su;Cho, Myeong-Woo;Choi, Won-Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.6
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    • pp.2624-2630
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    • 2013
  • In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead flame to provide enough strength for the next process. During the process, inspection processes are very important to detect exact locations of dispensed epoxy dots and to determine bonding status of dies whether they are lies at exact positions with sufficient bonding strength. In this study, a useful machine vision based inspection system is proposed for the LED die bonder. In the proposed system, 2 cameras are used for epoxy dot position detection and 2 cameras are sued for die attaching status determination. New vision processing algorithm is proposed, and its efficiency is verified through required field experiments. Measured position error is less than $X:-29{\mu}m$, $Y:-32{\mu}m$ and rotation error:$3^{\circ}$ using proposed vision algorithm. It is concluded that the proposed machine vision based inspection system can be successfully implemented on the developed die bonding system.

COG 플립칩 본딩 공정조건에 따른 Au-ITO 접합부 특성

  • Choe, Won-Jeong;Min, Gyeong-Eun;Han, Min-Gyu;Kim, Mok-Sun;Kim, Jun-Gi
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.05a
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    • pp.64.1-64.1
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    • 2011
  • LCD 디스플레이 등에 사용되는 글래스 패널 위에 bare si die를 직접 실장하는 COG 플립칩 패키지의 경우 Au 범프와 ITO 패드 간의 전기적 접속 및 접합부 신뢰성 확보를 위해 접속소재로서 ACF (anisotropic conductive film)가 사용되고 있다. 그러나 ACF는 고가이고 접속피치 미세화에 따라 브릿지 형상에 의한 쇼트 등의 문제가 발행할 수 있어 NCP (non-conductive paste)의 상용화가 요구되고 있다. 본 연구에서는 NCP를 적용한 COG 패키지에 있어서 온도, 압력 등의 열압착 본딩 조건과 NCP 물성이 Au-ITO 접합부의 전기적 및 기계적 특성에 미치는 영향을 조사하였다. NCP는 에폭시 레진과 경화제, 촉매제를 사용하여 다양하게 포뮬레이션을 하였고 DSC (Differential Scanning Calorimeter), TGA (Thermogravimetric Analysis), DEA (Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화 거동을 확인하였다. 테스트 베드는 면적 $5.2{\times}7.2\;mm^2$, 두께 650 ${\mu}m$, 접속피치 200 ${\mu}m$의 Au범프가 형성된 플립칩 실리콘 다이와 접속패드가 ITO로 finish된 글래스 기판을 사용하였다. 글래스 기판과 실리콘 칩은 본딩 전 PVA Tepla사의 Microwave 플라즈마 장비로 Ar, $O_2$ 플라즈마 처리를 하였으며, Panasonic FCB-3 플립칩 본더를 사용하여 본딩하였다. 본딩 후 접합면의 보이드를 평가하고 die 전단강도로 접합강도를 측정하였다.

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3D Integration using Bumpless Wafer-on-Wafer (WOW) Technology (Bumpless 접속 기술을 이용한 웨이퍼 레벨 3차원 적층 기술)

  • Kim, Young Suk
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.4
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    • pp.71-78
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    • 2012
  • This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

The Design of Zoom Microscope System for Inspecting Wire-Bonding (와이어 본딩 검사용 현미경 광학계의 설계)

  • 류재명;임천석;조재흥;정진호;전영세
    • Proceedings of the Optical Society of Korea Conference
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    • 2003.02a
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    • pp.256-257
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    • 2003
  • 반도체 와이어 본딩(wire-bonding) 조립공정에 사용되는 검사용 현미경 광학계를 설계하였다. 이러한 와이어는 리드프레임에 대해 $\pm$ 1 mm의 단차를 가진다. 이 때 리드프레임은 6배로 관찰하며, 와이어 부분은 2배로 관찰하고자 한다. 그러나 와이어의 단차로 인해 물체거리가 변하게 되며, 일반 광학계로는 배율도 변하게 된다. 물체거리가 변해도 동일한 배율을 가지는 광학계를 설계하기 위해 유한 물점용 3군 줌 광학계를 목적에 맞게 변형시켰다. (중략)

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