• The KIPS Transactions:PartC
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• v.11C no.2
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• pp.235-244
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• 2004

TCP Vegas version provides better performance and more stable services than TCP Tahoe and Reno versions, which are widely used in the current Internet. However, in the situation where TCP Vegas and Reno share the bottleneck link, the performance of TCP Vegas is much smaller than that of TCP Reno. This unfairness is due to the difference of congestion control mechanisms of each TCP use. Several studies have been executed in order to solve this unfairness problem. In this paper, we analyze the minimum window size to maintain the maximum TCP performance of link bandwidth. In addition, we propose an algorithm which maintains the TCP performance and improves fairness by selective packet drops in order to allocate proper window size of each TCP connections. To evaluate the performance of the proposed algorithm, we have measured the number of data bytes transmitted between end-to-end systems by each TCP connections. The simulation results show that the proposed algorithm maintains the maximum TCP performance and improves the fairness.

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.21-30
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• 2016

Recently manufacturing companies have used PLC control programs popularly for their automated production systems. Since the life cycle of production process is not so long, the change of the production lines occur frequently. Most of changes happen with modification of the position information and control process of the equipment. PLC control program is also modified based on the fundamental process. Therefore, to verify new PLC program by configuring virtual space according to real environment is needed. In this paper we show a logical modeling method, based on Timed-FSA useful for sequence control and dead-lock prevention. There is a problem wasting user's labor and time when defining a variety of states in a device. To overcome this problem, we propose an extended I-O model based on existing methods by adding a token concept of Petri Nets. Also we will show the usability of the extended I-O modeling through user study.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Journal of Convergence for Information Technology
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• v.11 no.8
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• pp.8-13
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• 2021

The purpose of this study is to propose a throughput costing as a performance measurement tool to measure cost indicators, which are one of the indicators for evaluating organizational performance in a smart factory manufacturing environment. An empirical study by questionnaire was conducted, and 60 experts were surveyed to verify the hypothesis. As a result of the study, it was concluded that the information provided based on throughput costing is helpful in cost measurement and in evaluating organizational performance efficiency and effectiveness, and it was confirmed that this method has usefulness to support the planning and control process. It is proposed that the use of throughput costing by constraint theory, which can maximize throughput and optimize inventory levels in the manufacturing process, can find solutions to bottlenecks affecting the efficiency and effectiveness of organizational performance.

• Korean Chemical Engineering Research
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• v.55 no.5
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• pp.609-617
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• 2017

Lignocellulosic biomass is a renewable resource for production of biofuels and biochemicals. Furfural (FF) is an important platform chemical catalytically derived from the hemicellulose fraction of biomass. Tetrahydrofurfuryl alcohol (THFA) is a FF derivative and can be used as an eco-friendly solvent with thermal and chemical stability. Despite large numbers of experimental studies for catalytic conversion of FF to THFA, few research have conducted on the economic feasibility for large-scale THFA production from FF. At the stage of assessment of the potential for commercialization of conversion technology, a large-scale process study is required to identify technological bottleneck and to obtain information for solving scale-up problems. In this study, process simulation and technoeconomic evaluation for catalytic conversion of FF to THFA are performed, as the following three steps: integrated process design, heat integration, and economic evaluation. First, a large-scale process including conversion and separation processes is designed based on experimental results. When the FF processing rate is 255 tonnes per day, the FF-to-THFA yields are 63.2~67.9 mol%. After heat integration, the heating requirements are reduced by 14.4~16.4%. Finally, we analyze the cost drivers and calculate minimum selling price of THFA by economic evaluation. The minimum selling price of THFA for the developed process are $2,120~2,340 per tonne, which are close to the current THFA market price.

• Journal of Korean Society of Environmental Engineers
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• v.28 no.9
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• pp.961-976
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• 2006

Designing water-reuse network which can reduce the fresh water within the process and increase the water-use efficiency by scientific and systematic analysis is recently interested in the industries. Water systems often allow efficient water uses via water reuse and recirculation in the paper, petrochemical, and steel industries which necessitate a lot of freshwater within the process. Defining network layout connecting water-using process is frequently accomplished by using water pinch technology which optimizes freshwater entering the process and also reduces the wastewater. In this review, recent researches and case studies of water pinch technology which can find the bottleneck of the water stream at the water reuse designing stage are introduced. Necessity of water pinch technology is illustrated by examples of real industries. Recent studies on simultaneous energy and water minimization and water-reuse network among industries in eco-industrial park(EIP) are also introduced.

• Korean Business Review
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• v.13
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• pp.263-273
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• 2000

Mercedes-Benz United States International (MBUSI) built a manufacturing facility for the production of the new M-Class All Activity Vehicle (AAV). This plant consists of three large sequential shops: the Body Shop, the Paint Shop, and the Assembly Shop. When the plant reaches full production, 270 vehicles will be produced each day by two shifts. A finished vehicle is intended to leave the end of the assembly line every 3.6 minutes. The main objective of this study is to simulate the design and operational policies of the AAV assembly facility and to verify that the daily throughput requirements can be met. The simulation study also answered the following questions: What is the maximum throughput (capacity) of the facility? What is the daily distribution of throughput? Does the current design produce the required throughput of 270 cars per day? How do the buffers behave in terms of quantity fluctuations? What are the possible bottlenecks to the desired throughput? This paper provides a description of the integrated simulation model to analyze the capability of the production facilities at MBUSI. This paper includes the inputs used for the development of each of the three individual models: the Body Shop, the Paint Shop, and the Assembly Shop. Additionally, it includes descriptions of the model features and the assumptions that were made.

• Journal of KIISE
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• v.42 no.9
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• pp.1162-1174
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• 2015

These days, the networks have exhibited HBDP (High Bandwidth Delay Product) characteristics. The legacy TCP slowly increases the size of the congestion window and drastically decreases the size of a congestion window. The legacy TCP has been found to be unsuitable for HBDP networks. TCP mechanisms for solving the problems of the legacy TCP can be categorized into the loss-based TCP and the delay-based TCP. Most of the TCP mechanisms use the standard slow start phase, which leads to a heavy packet loss event caused by the overshoot. Also, in the case of congestion avoidance, the loss-based TCP has shown problems of wastage in terms of the bandwidth and RTT (Round Trip Time) fairness. The delay-based TCP has shown a slow increase in speed and low occupancy of the bandwidth. In this paper, we propose a new scheme for improving the over shoot, increasing the speed of the bandwidth and overcoming the bandwidth occupancy and RTT fairness issues. By monitoring the buffer condition in the bottleneck link, the proposed scheme does congestion control and solves problems of slow start and congestion avoidance. By evaluating performance, we prove that our proposed scheme offers better performance in HBDP networks compared to the previous TCP mechanisms.

• Korean Chemical Engineering Research
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• v.51 no.1
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• pp.10-24
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• 2013

The state-of-arts of multiscale simulation (MSS) in science and engineering is briefly presented and MSS for process development (PD-MSS) is proposed to effectively apply the MSS to the process development. The four-level PD-MSS is composed of PLS (process-level simulation), FLS (fluid-level simulation), mFLS (microfluid-level simulation) and MLS (molecular-level simulation). Characteristics and methods of each level, as well as connectivity between the four levels are described. For example in PD-MSS, absorption column, fluidized-bed reactor, and adsorption process are introduced. For successful MSS, it is necessary to understand the multiscale nature in chemical engineering problems, to develop models representing physical phenomena at each scale and between scales, to develop softwares implementing mathematical models on computer, and to have strong computing facilities. MSS should be performed within acceptable accuracy of simulation results, available computation capacity, and reasonable efficiency of calculation. Macroscopic and microscopic scale simulations have been developed relatively well but mesoscale simulation shows a bottleneck in MSS. Therefore, advances on mesoscale models and simulation tools are required to accurately and reliably predict physical phenomena. PD-MSS will find its way into a sustainable technology being able to shorten the duration and to reduce the cost for process development.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.