• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.1-7
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• 2012

We have developed a new gate driver circuit for liquid crystal displays using oxide thin-film transistors (TFTs). In the new gate driver, negative gate bias is applied to turn off the oxide TFTs because the oxide TFT occasionally has negative threshold voltage (VT). In addition, we employed three parallel pull-down TFTs that are turned on in turns to enhance the stability. SPICE simulation showed that the proposed circuit worked successfully covering the VT range of -3 V ~ +6 V And fabrication results confirmed stable operation of the new circuit using oxide TFTs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.104-112
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• 2007

We developed a $7{\times}7$ parallel multiplier using LTPS-TFT. The proposed multiplier has multi-valued logic 7-3 Compressor with folding, 3-2 Compressor, and final carry propagation adder. Architecture minimized the carry propagation. And power consumption reduced by switching the current source to the circuit which is operated in current mode. The proposed multiplier improved PDP by 23%, EDP by 59%, and propagation delay time by 47% compared with Wallace Tree multiplier.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.80-86
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• 2003

Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1384-1385
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• 2008

본 논문에서는 내장된 수동형 트리플렉서와 듀얼 밴드/트라이모드 RF 모듈을 PCB에 내장시켜서 북미향 CDMA용 부품으로 제작하였다. 수동형 트리플렉서는 모든 수동 소자들을 다층 PCB 기판 안에 내장시키고 그 위에 GPS용 SAW 대역통과필터를 이용하여 설계 및 제작하였다. 8개의 인덕터와 커패시터로 이루어진 수동 회로는 다이플렉서와 병렬 공진기, 임피던스 매칭 회로로 구성되어 있다. CDMA용 듀얼밴드/트라이모드 RF 모듈은 트리플렉서와 CDMA, PCS용 듀플렉서를 테스트 보드 위에 조합하여 제작하였다. 측정된 주파수 특성들은 시뮬레이션 값과 비교적 일치하였다. 트리플렉서와 듀얼 밴드/트라이모드 RF 모듈은 각기 $3{\times}4mm^2$와 ${7\times}7mm^2$의 작은 크기였다. 설계 및 제작된 소자들은 고성능과 경박단소화, 저가화 등의 이점이 있기 때문에, 북미향 CDMA용 단말기의 응용부품에 적용될 수 있을 것으로 예상된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.752-757
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• 2006

In the case of the requirement of high speed transmission, OFDM is a powerful technique employed in communications systems suffering from frequency selective fading. In this paper, we apply an optimal adaptive bitloading algorithm technique. The BER performance of the fixed-rate SISO and adaptive SISO is simulated. Specially, we can decompose the MIMO channel into the SISO channel by making use of the singular value decomposition(SVD) assuming channel knowledge in a multipath environment. As a results of simulation, we confirmed that the BER enhancement of MIMO-OFDM system with the bitloadins algorithm was superior to the SISO-OFDM system.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.504-507
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• 2006

현재 LCD(Liquid Crystal Display)용 광원으로서 주로 냉음극 방전램프(CCFL : Cold Cathode Fluorescent Lamp)가 사용되고 있으며, 그 외 LED를 비롯해서 외부전극 방전램프(EEFL: External Electrode Fluorescent Lamp), 면광원(FFL : Flat Fluorescent Lamp), 전계 방출램프(FEL : Field Emission Lamp)등 다른 광원에 대한 적용도 활발히 진행되고 있다. 본 논문에서는 멀티램프 구동이 유리하여 인버터 개수를 줄일 수 있는 장점을 가지고 있는 EEFL을 사용하였으며, 변압기의 자체 손실을 줄이고 소형화가 가능하며, 높은 승압 비를 갖는 압전 변압기를 병렬로 연결하여 멀티램프 구동이 가능하도록 하였다. 최적의 EEFL 구동회로를 구성하기 위해서 Push-Pull 타입의 압전 인버터를 설계하였으며, 설계된 인버터 회로에 대한 시뮬레이션 분석을 수행하고, 향후 여러 형태의 구동 방법을 적용하므로 서 압전 변압기로도 대화면 멀티 램프 구동용 인버터의 제작이 가능함을 제시하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.4
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• pp.403-408
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• 2000

In this paper, voltage control APF(Active Power Filter) is introduced to improve power factor and reduce harmonics generated from nonlinear load. The voltage controlled APF which is consisted of inverter and passive filter operates with nonlinear load simultaneously. Real power supplies from main power to load and reactive power provides from APF to load. According to the results o experiment and simulation, it is proved that the proposed system has the performance of improving power factor and reducing harmonics.

• Journal of IKEEE
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• v.24 no.3
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• pp.890-894
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• 2020

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.749-755
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• 2003

Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.