Browse > Article

Multiplier Using CRT and Overlapped Multiple-bit Scanning Method  

김우완 (경남대학교 정보통신공학부)
장상동 (경남대학교 컴퓨터공학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.30, no.12, 2003 , pp. 749-755 More about this Journal
Abstract
Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.
Keywords
CRT; CRT; Multiplier; Overlapped Multiple-bit Scanning Method;
Citations & Related Records
연도 인용수 순위
  • Reference
1 /
[ Kai Hwang ] / Computer Arithmetic Principles, Architecture, and Design
2 Khalid M. Ibrahim., and Salam N.Saloum, 'An efficient residue to binary converter design,' IEEE Trans on Circuit and System, vol., 35, No.9, pp. 1156-1158, September, 1988   DOI   ScienceOn
3 A. Hiasat 'New designs for a sign detector and a residue to binary converter,' lEE Proceedings-G, vol. 140, No.4, pp. 247-252, August 1993   DOI   ScienceOn
4 Ahmad A. Hiasat, 'New Efficient Structure for a Modular Multiplier for RNS,' IEEE Trans Computers, vol. 49, pp. 170-174, Feb. 2000   DOI   ScienceOn
5 F. Pourbigharaz, Memver, IEEE and RM Yassine, 'A Signed-Digit Architecture for Residue to Binary Transformation,' Algorithmica, pp. 79-119, 3, 1988   DOI   ScienceOn
6 Kai Hwang, 'Computer Arithmetic Principles, Architecture, and Design,' School of Electrical Engineering Purdue University, 1979
7 Braun, E. L., Digital Computer Design, Academic Press, New York, 1963
8 Khaled M. Elleithy, Member, IEEE, and Magdy A. Bayourni, Senior Member, IEEE, 'Fast and Flexible Architectures for RNS Arithmetic Decoding,' IEEE Transaction on Circuits and Systems, vol. 39, No.4, pp. 226-235, April 1992   DOI
9 K. Elleithy and M. Bayoumi, 'A Systolic Architecture for modulo Multiplication,' IEEE Trans Circuit and System- II: Analog and Digital Signal Processing, vol. 42, pp. 7'2!5-729, Nov. 1995   DOI   ScienceOn
10 W. K. Jenkins, 'Techniques for residue to analog conversion for residue encoded digital filters,' IEEE Trans, Circuits Syst., vol. CAS-25, pp 553-562, July 1978
11 A. Wrzyszcz, D. Milford, and E. Dagless, 'A New Approach to fixed-Coefficient Inner Product Computation over Finite Rings,' IEEE Trans Computers, vol. 45, pp. no. 12, pp. 1,345-1,355, Dec. 1996   DOI   ScienceOn
12 A. A Sawchuk and T. C Strand, 'Digital optical computing,' Proc IEEE, Vol. 72, pp. 758-779, July 1982
13 J. Bajard, L. Didier, and P. Kornerup, 'An RNS Montgomery Modular Multiplication Algorithm,' IEEE Trans Computers, vol. 47, pp. 766-776, July. 1998   DOI   ScienceOn
14 H. M. Razavi, and J. Battelini., 'Design of a residue arithmetic multiplier,' lEE Proceedings-G, vol. 139, No.5, pp. 581-585, October 1992   DOI   ScienceOn