• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.3
• /
• pp.85-90
• /
• 2015

In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.

• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.5
• /
• pp.147-152
• /
• 2015

In general, there are two synchronization methods in parallel event-driven simulation, pessimistic approach and optimistic approach. In this paper, we propose a new approach, sporadic synchronization combining both for prediction-based parallel event-driven logic simulation. We claim this hybrid solution is pretty effective to minimize both checkpoint overhead and restart overhead, which are related problems with frequent false predictions for improving the performance of the prediction-based parallel event-driven logic simulation. The experiment has clearly shown the advantage of the proposed approach.

• KIPS Transactions on Computer and Communication Systems
• /
• v.8 no.3
• /
• pp.57-64
• /
• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• KIPS Transactions on Computer and Communication Systems
• /
• v.5 no.12
• /
• pp.439-446
• /
• 2016

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.

• Proceedings of the KIPE Conference
• /
• 2010.07a
• /
• pp.534-535
• /
• 2010

최근 전원장치의 대용량화가 요구되면서 하나의 전원에서 모든 전력을 부담하는 것보다 여러 대의 전원을 병렬 운전하여 신뢰성을 높이고 용량을 증대시키는 방안이 연구되고 있다. 본 논문에서는 병렬 연결된 전원장치에 부하전류 분배를 하는데 있어 디지털 방식을 사용하여 고속 통신을 통한 제어를 이루어 시스템 비용을 낮추고 높은 수준의 제어 로직을 구성하여 부하 변동시 안정된 부하분담이 이루어지는 모듈화 된 일정 용량의 전원 장치를 제안하고 시뮬레이션을 통하여 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.12
• /
• pp.27-35
• /
• 1999

In a typical spread spectrum system, parallel correlator occupies a large fraction of power consumption because of the large number of accumulators in the system. In this paper, a novel accumulator is proposed that can reduce the power consumption in the parallel correlator. The proposed accumulator counts the numbers of 1 of the incoming input data. The counted values are weighted and added together to obtain the final correlation value only at the end of the accumulation. The proposed accumulator has been designed and simulated by CADENCE Verilog-XL and synthesized by SYNOPSYS Design Compiler with $0.6{\mu}m$ standard cell library. Power consumption results have been obtained from EPIC PowerMill simulations. Simulation results are very encouraging. First, the power dissipation is reduced by 22% and the maximum operating frequency is increased by 323%. In addition, the parallel correlator using the proposed accumulators consumed less power than the conventional active parallel correlators by 22%, and less power than the conventional passive correlator by 43%.

• Proceedings of the IEEK Conference
• /
• 2000.09a
• /
• pp.255-258
• /
• 2000

본 논문에서는 효율적인 면적의 저전력 FIR 필터를 제안한다. 제안된 필터는 6 비트 8 탭의 구조를 갖는PRML(Partial-Response Maximum Likelihood) 디스크드라이브 read channel용 FIR 필터이다 제안된 구조는 병렬연산 구조를 채택하고 있으며 네 단의 파이프라인 구조를 가지고 있다. 곱셈을 위하여 부스 알고리즘이 사용되며 압축기를 이용하여 덧셈을 수행한다. 저전력을 위해 CMOS 패스 트랜지스터를 사용하였으며 면적을 줄이기 위해 single-rail 로직을 사용하였다 제안된 구조를 0.65㎛ CMOS 공정을 이용하여 설계하였으며1.88 × 1.38㎟의 면적을 차지하였고 HSPICE 시뮬레이션 결과 3.3V의 공급전압에서 100㎒로 동작시 120㎽의 전력을 소모한다. 제안된 구조는 기존의 구조들에 비해 약 11%의 전력이 감소했으며 약 33%의 면적이 감소하였다.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.37 no.3
• /
• pp.307-312
• /
• 2013

The interest in reducing the emissions and increasing the fuel economy of ICE vehicles has prompted research on hybrid vehicles, which come in the series, parallel, and power-split types. This study focuses on the series-type hybrid electric vehicle, which has a simple structure. Because each component of a series hybrid vehicle is larger than the corresponding component of the parallel type, the sizing of the vehicle is very important. This is because the performance may be greater or less than what is required. Thus, in this research, the optimal fuel economy was determined and simulated in a real-world system. The optimal sizing was achieved based on the motor, engine/generator, and battery for 13 cycles, where DP was used. The model was developed using ASCET or a Simulink-Amisim Co-simulation platform on the rapid controller prototype, ES-1000.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.1
• /
• pp.170-178
• /
• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.11
• /
• pp.21-30
• /
• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.