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http://dx.doi.org/10.3745/KTCCS.2015.4.3.85

A New Prediction-Based Parallel Event-Driven Logic Simulation  

Yang, Seiyang (부산대학교 정보컴퓨터공학부)
Publication Information
KIPS Transactions on Computer and Communication Systems / v.4, no.3, 2015 , pp. 85-90 More about this Journal
Abstract
In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.
Keywords
Verification; Event-Driven Simulation; Parallel Simulation;
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  • Reference
1 R. M. Fujimoto, "Parallel Discrete Event Simulation," Communication of the ACM, Vol.33, No.10, pp.30-53, Oct., 1990.
2 D. M. Nicol, "Principles of Conservative Parallel Simulation," Proceedings of the 28th Winter Simulation Conference, pp.128-135, 1996.
3 R. M. Fujimoto, "Time Warp on a Shared Memory Multiprocessor," Transactions of the Society for Computer Simulation, Vol.6, No.3, pp.211-239, Jul., 1989.
4 L. Li, C. Tropper, "A design-driven partitioning algorithm for distributed Verilog simulation," in Proc. 20th International Workshop on Principles of Advanced and Distributed Simulation (PADS), pp.211-218, 2007.
5 D. Chatterjee, A. DeOrio, and V. Bertacco, "Event-driven gate-level simulation with general purpose GPUs," Proceedings of Design Automation Conference(DAC09), pp.557-562, Jun., 2009.
6 IUS Simulator Usermanual, Cadence Design Systems [Internet], http://www.cadence.com
7 VCS Simulator Usermanual, Synopsys [Internet], http://www.synopsys.com
8 K. Chang, C. Browy, "Parallel Logic Simulation: Myth or Reality?," Computer, Vol.45, No.4, pp.67-73, Apr., 2012.   DOI
9 D. Chatterjee, A. DeOrio, and V. Bertacco, "High-performance gate-level simulation with GP-GPUs," Proceedings of the Conference on Design Automation and Test in Europe (DATE'09), pp.1332-1339, Apr., 2009.
10 Yuhao Zhu, Bo Wang, and Yangdong Deng, "Massively Parallel Logic Simulation with GPUs," ACM Transactions on Design Automation of Electronic Systems(TODAES), Vol.16, No.3, pp.1-20, Jun., 2011.
11 Nanjundappa, M., Patel, H., Jose, B. A., and Shukla, S., "SCGPSim: A Fast SystemC Simulator on GPUs," In Proceedings of the 15th Asia and South Pacific Design Automation Conference(ASPDAC'10), pp.145-154, 2010.