• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of Internet Computing and Services
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• v.21 no.4
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• pp.117-126
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• 2020

A maritime object detection system is an intelligent assistance system to maritime autonomous surface ship(MASS). It detects automatically floating debris, which has a clash risk with objects in the surrounding water and used to be checked by a captain with a naked eye, at a similar level of accuracy to the human check method. It is used to detect objects around a ship. In the past, they were detected with information gathered from radars or sonar devices. With the development of artificial intelligence technology, intelligent CCTV installed in a ship are used to detect various types of floating debris on the course of sailing. If the speed of processing video data slows down due to the various requirements and complexity of MASS, however, there is no guarantee for safety as well as smooth service support. Trying to solve this issue, this study conducted research on the minimization of computation volumes for video data and the increased speed of data processing to detect maritime objects. Unlike previous studies that used the Hough transform algorithm to find the horizon and secure the areas of interest for the concerned objects, the present study proposed a new method of optimizing a binarization algorithm and finding areas whose locations were similar to actual objects in order to improve the speed. A maritime object detection system was materialized based on deep learning CNN to demonstrate the usefulness of the proposed method and assess the performance of the algorithm. The proposed algorithm performed at a speed that was 4 times faster than the old method while keeping the detection accuracy of the old method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2000.05a
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• pp.101-106
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• 2000

자동화 기기 분야에서 컴퓨터의 적용 및 응용은 하드웨어 발달에 따라 매우 빠르고 민감하게 반영되어왔다. 이는 컴퓨터 하드웨어의 빠른 개발 주기에 맞춰 저 가격, 고 효율성, 높은 신뢰성, 호환성 등의 장점을 가진 PC가 현대의 컴퓨터 흐름을 주도하게 되면서 자동화 산업분야 또한 이를 적용하여 왔기 때문이다. 이에 따라, 자동화 기기 분야에서는 고 가격, 긴 개발기간 등을 필요로 했던 과거와 달리 저 가격, 짧은 개발기간, 다양한 개발환경 등을 이룰 수 있었다. 또한, 생산량 증가에만 의존하던 과거와 달리 현대에 이르러서는 시스템의 최적화, 효율의 극대화, 시스템의 안정성, 운용의 편리성, 호환성 등의 개념들이 도입되고 있는 것이다. 자동화 기기를 구성하는 요인으로는 크게 시스템의 틀을 이루는 기계부분과 이를 제어하는 제어 시스템부로 나뉠 수 있다. 제어 시스템에서는 기계부분의 동작을 제어하는 동작 제어부와 이에 관한 정보를 화면에 나타내는 GUI(Graphical User Interface)부분으로 나뉘게된다. 현재에는 이를 통합하여 하나의 하드웨어에서 제어부와 GUI를 모두 담당하는 방법이 연구 진행되고 있으나, 하드웨어를 둘로 나누거나 하나로 하여도 제어부와 GUI 사이의 통신부분은 빼놓을 수 없는 요소가 된다. 따라서, 본 논문에서는 시스템의 안정성을 위하여 두 시스템간에 송·수신되는 데이터를 추적할 수 있도록 하는 Emulate 기법을 구현 및 개발하고자 한다. 이는, 두 시스템간의 통신 데이터를 실시간으로 누적, 저장하여 사용자로 하여금 시스템의 운용상태를 분석할 수 있게 하였으며, 시스템 오류발생 시 Emulate 자료를 근거로 시스템의 운용상태를 파악할 수 있게 하였다.근 제한기능을 제공하며 각 클라이언트와 서버간의 실시간 연결 혹은 지연연결을 지원하는 독립적인 애플리케이션이다. 이러한 처방전달 메시징시스템을 구성하는 각 요소에 대해 정의하고 개념적 모델을 설계하고자 한다.에게 청구되며, 소비자에게 전송 되는 청구서는 사용자DB를 참조하여 사용자가 미리 정의한 원하는 형태로 변환되어 전달되며, 필요시 암호화 과정을 거치는 것이 가능해야 한다. 전송된 청구서는 전자우편의 경우, 암호해독이 가능한 전용 브라우저를 통해 열람 되며, 이는 다시 전용 브라우저를 통해 지불인증이 승인되어 청구 제시서버에게 전송된다. EBPP 시스템의 제어 흐름은 크게 기업이 청구 정보를 소비자에게 제시하는 흐름과 소비자의 지불 승인으로 인해 기업이 은행에 지불을 요구하는 흐름으로 구분할 수 있다. 본 논문에서는 통합 청구서버 및 정구 제시서버의 역할 및 구성 요소들에 대해 서술하고, EBPP 시스템과 연동하여야 하는 메일 서버와의 상호 작용에 대해 서술할 것이다. 본 시스템을 아직 구현이 되지 않은 관계로 시스템의 성능 등의 수치적 결과를 제시할 수 없는 상태다., 취약계층을 위한 일차의료, 의약관리), ${\circled}2$ 보건소 조직 개편 및 민간의료기관과 협력체계 확립, ${\circled}3$ 전문인력 확보 및 인력구성 조정, 그리고 ${\circled}4$ 방문보건사업의 강화 등이다., 대사(代謝)와 관계(關係)있음을 시사(示唆)해 주고 있다.ble nutrient (TDN) was highest in booting stage (59.7%); however no significant difference was foun

• KIPS Transactions on Software and Data Engineering
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• v.6 no.2
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• pp.103-116
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• 2017

In this paper, we present the design and implementation of a large-scale qualitative spatial reasoner, which can derive new qualitative spatial knowledge representing both topological and directional relationships between two arbitrary spatial objects in efficient way using Aparch Spark SQL. Apache Spark SQL is well known as a distributed parallel programming environment which provides both efficient join operations and query processing functions over a variety of data in Hadoop cluster computer systems. In our spatial reasoner, the overall reasoning process is divided into 6 jobs such as knowledge encoding, inverse reasoning, equal reasoning, transitive reasoning, relation refining, knowledge decoding, and then the execution order over the reasoning jobs is determined in consideration of both logical causal relationships and computational efficiency. The knowledge encoding job reduces the size of knowledge base to reason over by transforming the input knowledge of XML/RDF form into one of more precise form. Repeat of the transitive reasoning job and the relation refining job usually consumes most of computational time and storage for the overall reasoning process. In order to improve the jobs, our reasoner finds out the minimal disjunctive relations for qualitative spatial reasoning, and then, based upon them, it not only reduces the composition table to be used for the transitive reasoning job, but also optimizes the relation refining job. Through experiments using a large-scale benchmarking spatial knowledge base, the proposed reasoner showed high performance and scalability.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.224-238
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• 2004

Multi-modality image registration is a widely used image processing technique to obtain composite information from two different kinds of image sources. This study proposes an image registration method based on moment information and surface distance, which improves the previous surface-based registration method. The proposed method ensures stable registration results with low registration error without being subject to the initial position and direction of the object. In the preprocessing step, the surface points of the object are extracted, and then moment information is computed based on the surface points. Moment information is matched prior to fine registration based on the surface distance, in order to ensure stable registration results even when the initial positions and directions of the objects are very different. Moreover, surface comer sampling algorithm has been used in extracting representative surface points of the image to overcome the limits of the existed random sampling or systematic sampling methods. The proposed method has been applied to brain MRI(Magnetic Resonance Imaging) and PET(Positron Emission Tomography), and its accuracy and stability were verified through registration error ratio and visual inspection of the 2D/3D registration result images.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.104.1-104.1
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• 2011

가볍고, 유연성(flexibility)을 갖는 박막(thin film)형 플랙서블 태양전지(flexible solar cell)는 상황에 따른 형태의 변형이 가능하여, 휴대가 간편하고, 기존 혹은 신규 구조물의 지붕(rooftop)등에 설치가 용이하여, 차세대 성장 동력 분야에서 각광받고 있다. 그러나 아직까지 플랙서블 태양전지는 제작시 열에 의한 기판의 변형, 기판 이송시 너울 현상, 대면적 패터닝(patterning) 기술 등 많은 어려움 등으로 웨이퍼나 글라스 기판에 제조된 태양전지 대비 낮은 광전환 효율을 갖는다. 따라서 본 연구에서는 플랙서플 태양전지 성능개선을 위해 3.5세대급 ($450{\times}450cm^2$) 스퍼터(sputter), 금속유기 화학기상장치 (MOCVD), 플라즈마 화학기상장치 (PECVD), 레이저 가공장치 (Laser scriber)를 이용하여 a-Si:H/a-SiGe:H 이중접합(tandem)을 갖는 태양전지를 제작하였고, 광 변환효율 특성을 평가하였다. 전도도(conductivity), 라만(Raman)분광 및 UV/Visible 분광 분석을 통하여 박막의 전기적, 구조적, 광학적 물성을 평가하여 단위박막의 물성을 최적화 했다. 또한 제작된 태양전지는 쏠라 시뮬레이터 (Solar Simulator)를 이용하여 성능 평가를 수행하였고, 상/하부층의 전류 정합 (current matching)을 위해 외부양자효율 (external quantum efficiency) 분석을 수행하였다. 제작된 이중접합 접이식 태양전지로 소면적($0.25cm^2$)에서 8.7%, 대면적($360cm^2$ 이상) 8.0% 이상의 효율을 확보하였으며, 성능 개선을 위해 대면적 패턴 기술 향상 및 공정 기술 개선을 수행 중이다.

• Journal of the Korean Society for Nondestructive Testing
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• v.31 no.5
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• pp.552-559
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• 2011

Recently, the eddy current testing(ECT), alternating current field testing, magnetic flux leakage testing and remote field testing have been used as a nondestructive evaluation method based on the electromagnetic induction phenomenon. The eddy current testing is now widely accepted as a NDE method for the heat exchanger tube in the electric power industry, chemical, shipbuilding, and military. The ECT system mainly consists of the synthesizer module, analog module, analog-to-digital converter, power supplier, and data acquisition and analysis program. In the previous study, the synthesizer module and the analog module which is essential to the ECT system were primarily developed, and in this study the data acquisition and analysis program were developed. The operation system for this program is based on the Windows 7, and optimized for the Korean users, and the specific feature of this program using setup wizard enables inspector to make a setup easily for acquisition and analysis of ECT data. In this paper, the configuration and functions of eddy current data acquisition and analysis program will be introduced.