• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.506-515
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• 1990

The major purpose of this thesis is suggest the simulation algorithm for performance analysis of throughput of slotted 1-persistent CSMA/CD bus protocol in Local Area Networks. The suggested simulation algorithm processes the effect of each station group that classified by the number of collision experience. Therefore, this simulation algorithm is more effective in terms of the execute than existing algorithm that processed the effect of each station. This study suggests the method for application to the busy/idle generator.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.573-574
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• 2009

열차 통신의 목적은 분산 제어 시스템에서 빠르고 정확한 데이터 교환에 있다. 이를 위하여 개발되고 1999년 IEC와 IEEE에 의해 국제 규격으로 승인된 TCN(Train Communication Network)은 차량간 통신 버스인 WTB(Wired Train Bus)와 차량내 통신 버스인 MVB(Multifunction Vehicle Bus)의 이중 계층 구조로 구성되며 TCN의 데이터 서비스는 프로세스 데이터, 메시지 데이터, 관리용 데이터의 세가지 데이터 서비스로 구분된다. MVB는 전송 가능한 데이터 서비스에 따라 디바이스의 클래스가 나눠지게 된다. 본 논문에서는 MVB에서 버스 마스터의 프레임에 따라 데이터를 보낼 수 있는 슬레이브 컨트롤러의 구성과 시뮬레이션을 통해 구현된 장치의 기능이 국제 표준의 제안사항들을 따르고 있는 지 증명한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.288-299
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• 1993

This paper proposes the new bus protocol in the tightly coupled multiprocessor system. The bus protocol uses the pipelined data transfer and block transfer scheme to increase the bus bandwidth, The bus also has the independent transfer lines for the address and data respectively, and it can transfer the data up to maximum 264 Mbytes /sec. This paper also models the multiprocessor system where each processor boards have the private cache. Simulation evaluates the bus and system performance according to hit ratio of the reference data in cache memory, In the case of using this bus, the bus is evaluated not to be saturated when up to 10 processor boards are connected to the bus. As for up to 4 memory interleavng, the performance increases linearly.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.207-215
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• 2004

In a hierarchical-bus multiprocessor system, cache coherence protocol has effect on system performance. Under a particular cache coherence protocol, system performance can be affected by bus bandwidth, memory size, and memory block size. Therefore sensitivity analysis is necessary for the part of multiprocessor system. In this paper, we set up cache coherence protocol for hierarchical-bus multiprocessor system, and compute probability of state of protocol, and analyze sensitivity for part of system by simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.78-88
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• 1990

To evaluate the performance of a multiprocessor system, a discrete event model of memory interference in the system employing multiple-bus interconnection networks is proposed. An analytic model of the system is presented and then simulator models are implemented for cross-verifying the analytic results and simulation results. The simulator model takes as input the number of processors, the number of memory modules, the number of buses and the local memory miss ratio. The model produces as output the memory bandwidth, the processor, memory module and bus utilization and the bus contention ratio. Using the model in the design of the system, it is possible to evaluate the system performance by analyzing the interaction of the input parameters.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.547-554
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• 2002

This paper proposes an efficient dynamic routing algorithm for Multistage Bus Networks(MBN's) in distributed shared memory environment. Our algorithm utilizes extra paths available on MBN and determines routing paths adaptively according to switch traffic in order to distribute traffic among switches. Precisely, a packet is transmitted to the next switch on an extra path having a lighter traffic. As a consequence the proposed algorithm reduces the mean response time and the average number of waiting tasks. The results of simulations, carried out with varying numbers of processors and varying switch sizes, show that the proposed algorithm improves the mean response time by 9% and the average number of waiting tasks by 21.6%, compared to the existing routing algorithms which do not consider extra paths on MBN.

• Journal of Korean Society of Transportation
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• v.18 no.3
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• pp.43-54
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• 2000

이 연구는 버스정보 시스템 설계에 필요한 운행시격 결정과 통행시간 예측을 위한 알고리즘 개발을 다룬다. 운행시격 결정 문제는 버스와 같은 대중교통 수단을 운영하는데 중요한 요소 중에 하나이다. 기존 연구는 버스 운행비용과 승객비용의 합을 최소로 하는 운행시 격을 찾는데 초점을 두고 이다. 이때 승객비용이란 승객 대기비용과 승객 교통비용의 합으로 이루어진다. 그런데 우리나라와 같이 버스회사 수입이 전액 운행수입에만 의존하는 경우엔 이러한 접근 방식이 타당하지 않다. 기존의 방식과 다르게 승객비용으로 승객 이탈비용을 사용하여 버스의 최적 운행시 격을 구하는 것이 이 연구의 목적이다. 먼저 정류장이 하나인 경우에 대해 해석적 방법으로 풀고, 정류장이 여러 개인 경우에 대해서는 시뮬레이션 기법을 적용한다. 또한 이 연구는 신뢰성이 높고 정확한 통행시간 예측정보를 산출하기 위해 2 단계 예측 기법과 전문가시스템을 이용하는 자료융합 알고리즘을 개발한다. 정확한 정보를 제공하려면 교통정보 수집원을 통해 얻는 자료가 정확해야 하고, 또한 교통상황 변화에 따라 실시간으로 통행시간을 예측하는 것이 필요하다. 이 연구는 AVL(Automatic Vehicle Location)시스템을 이용한 버스정보시스템에서 실시간 데이터와 과거 데이터를 융합하여 통행시간을 예측하는 알고리즘을 개발한다. AVL 데이터를 수집하는 과정에서는 경제성을 고려하여 데이터를 수집한다. 그리고, 버스의 운행관리와 정확한 도착예정시간을 예측하기 위해 AVL시스템을 통해 얻은 데이터의 패턴을 분석하고 유고상황을 감지한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of Korean Society of Transportation
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• v.30 no.4
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• pp.21-32
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• 2012

Exclusive bus lane (EBL) is typically located in the roadway median, and is accessed by weaving across the GPLs(general purpose lanes) before entering from the left lane of the GPLs. To maximize the potential for successful EBL operations, a critical design issue that requires special attention is the length of bus weaving section before entering EBL. The process of developing guidelines for the length of bus weaving section can be supported by a sensitivity analysis of performance measure (safety) with respect to the bus weaving distance. However, field data are difficult to obtain due to inherent complexity in creating performance measure (safety) samples under various interesting flows and bus weaving distance that are keys to research success. In this paper, VISSIM simulation is applied to simulate the operation of roadway weaving areas with EBL, and based on vehicle trajectory data from microscopic traffic simulation models, the Surrogate Safety Assessment Model (SSAM) computes the number of surrogate conflicts (or degree of safety) with respect to the bus weaving distance. Then, a multiple linear regression (MLR) model using safety data (number of surrogate conflicts) is developed. Finally, guidelines for bus weaving distance are established based on the developed MLR. Developed guidelines explicitly indicate that a longer bus weaving distance is required to maintain desired safety as weaving volume increases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.