• Journal of Advanced Marine Engineering and Technology
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• v.28 no.4
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• pp.624-631
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• 2004

The experimental study on heat transfer characteristics of protruding heated block array as conducted to investigate and to compare the performance of impinging single circular jet in fully developed tube with a twisted tape as a swirl generator. The effects of jet Reynolds number(Re=8700, 13800, 20000. 26500), dimensionless jet-to-block distance(H/d=1. 3, 5. 7) and swirl number(S=0.11, 0.23, 0.30) of the swirl jet on the average Nusselt number for each block and all blocks have been examined. Measurements of heat transfer rate on block surfaces were used naphthalene sublimation technique. Mean velocity and turbulence intensity of the jet along the axis were measured. Potential core length of the jet was 5 times of nozzle diameter because it was fully developed and initially turbulent. With the twisted tape in the nozzle, heat transfer coefficients were higher than those without the twisted tape. which are mainly caused with increasing the jet Reynolds number and swirl number.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.613-624
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• 2011

An MMIC multi-function chip for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. A digital serial-to-parallel converter is included in this chip in order to reduce the number of the control interface. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a relative compact size of 24 $mm^2$(6 mm${\times}$4 mm) exhibits a transmit/receive gain of 24/15 dB and a P1dB of 21 dBm from 8.5 GHz to 10.5 GHz. The RMS errors for the 64 states of the 6-bit phase shift and attenuation were measured to $7^{\circ}$ and 0.3 dB, respectively over the frequency.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.71-76
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• 2012

A chip interconnection technology for smart fabrics was investigated by using flip-chip bonding of SnBi low-temperature solder. A fabric substrate with a Cu leadframe could be successfully fabricated with transferring a Cu leadframe from a carrier film to a fabric by hot-pressing at $130^{\circ}C$. A chip specimen with SnBi solder bumps was formed by screen printing of SnBi solder paste and was connected to the Cu leadframe of the fabric substrate by flip-chip bonding at $180^{\circ}C$ for 60 sec. The average contact resistance of the SnBi flip-chip joint of the smart fabric was measured as $9m{\Omega}$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Food Engineering Progress
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• v.14 no.1
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• pp.49-53
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• 2010

Surface plasmon resonance (SPR) which is utilized in thin film refractometry-based sensors has been concerned on measurement of physical, chemical and biological quantities because of its high sensitivity and label-free feature. In this paper, an application of SPR to detection of alcohol content in wine and liquor was investigated. The result showed that SPR sensor had high potential to evaluate alcohol content. Nevertheless, food industry may need SPR sensor with higher sensitivity. Herein, we introduced a nano-technique into fabrication of SPR chip to enhance SPR sensitivity. Using Langmuir-Blodgett (LB) method, gold film with nano-structured surface was devised. In order to make a new SPR chip, firstly, a single layer of nano-scaled silica particles adhered to plain surface of gold film. Thereafter, gold was deposited on the template by an e-beam evaporator. Finally, the nano-structured surface with basin-like shape was obtained after removing the silica particles by sonication. In this study, two types of silica particles, or 130 nm and 300 nm, were used as template beads and sensitivity of the new SPR chip was tested with ethanol solution, respectively. Applying the new developed SPR sensor to a model food of alcoholic beverage, the sensitivity showed improvement of 95% over the conventional one.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.5
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.63-71
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• 2000

Infrared (IR) detector chip, which detects the IR radiation from all of the objects and converts to image signal, is usually fabricated using hybrid bonding technology with detector away and readout integrated circuit (ROIC). In this study, we designed the readout circuit and simulated its operations. Fabricating readout circuit chips, we measured operation results satisfying its design requirements in 6V supply voltage. After we mount the IR detector chip in the manufactured thermal image system, thermal images were implemented. The obtained thermal images for high and room temperature target objects are sufficiently recognizable. Using the low noise thermal Image system, we expect to obtain thermal images with higher temperature resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.361-366
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• 2004

보청기에서 마이크로폰을 여러 개 배치하여 소음 감소 효과를 가져 올 수 있다. 본 논문에서는 양측 귀에 각각 두개씩의 보청기용 마이크로폰을 배치했을 때의 효과를 경계 요소 기법에 의해 해석하였다. 두개의 마이크로폰을 배열하여 마이크로폰 두개 사이의 시간 지연에 의한 특별한 지향성 패턴을 만들게 되고, 이러한 지향성 패턴은 기하학적으로 소음 대 잡음의 비를 증가시킬 수 있다. 두 개의 마이크로폰 배열에 의한 3차원 지향성 패턴 해석에 경계요소기법이 응용되었으며, 이러한 수치 해석은 보청기 DSP칩의 시간 지연 파라미터 계산에 이용될 수 있다. 두 개 마이크로폰사이의 간격은 10mm로 고정시키고, 머리의 전 방향에 폭이 좁은 지향패턴이 생기도록 두 개 마이크로폰의 사이 시간 지연을 바꾸어 주었다. 시간 지연의 변화를 입력 주파수에 따라 관찰하였다.