• Journal of The Korean Association of Information Education
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• v.17 no.1
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• pp.9-21
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• 2013

The purpose of this paper is to develop and implement a mobile application system to improve arithmetical operations for low achievers. The proposed system has the following characteristics. First, the system provides individual study for low achievers based on their different study levels. Second, instant feedback can be provided to students for maintaining study motivation. Third, the system enables students to study arithmetical operations in persistent and repetitive manner. This is due to that, in the literature, arithmetical operation capacity can be increased by persistent and repetitive practices. The proposed system is applied to mathematics low achievers and the following results are obtained. First, interests and intrinsic motivation are increased through use of the proposed system. Second, arithmetical operation speed is increased. Also, accuracy of arithmetical operation is improved. Thus, it is concluded that arithmetical operation capacity of low achievers is improved using the proposed system.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.9-18
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• 2010

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.10
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• pp.1020-1023
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• 2011

In this paper, we present a symbol remapping method of BRGC M-ary QAM signal by using LLR soft bit decision information which is obtained after iterative decoding process. In order to reconstruct estimated transmitted signal constellation, we have to use exponential or hyperbolic tangent(tanh) function resulting in high implementation complexity. The BRGC mapping rule enables us to use a recursive operation. In addtion, we reduce the implementing complexity by using a curve fitting algorithm.

• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.390-395
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• 2001

In this paper, we propose a fast warping prediction using bit-pattern for motion estimation. Because of the spatial dependency between motion vectors of neighboring node points carrying motion information, the optimization of motion search requires an iterative search. The computational load stemming from the iterative search is one of the major obstacles for practical usage of warping prediction. The motion estimation in the proposed algorithm measures whether the motion content of the area is or not, using bit-pattern. Warping prediction using the motion content of the area make the procedure of motion estimation efficient by eliminating an unnecessary searching. Experimental results show that the proposed algorithm can reduce more 75% iterative search while maintaining performances as close as the conventional warping prediction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.743-747
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• 2010

This paper presents an iterative adaptive hybrid image restoration algorithm for fast convergence. The local variance, mean, and maximum value are used to constrain the solution space. These parameters are computed at each iteration step using partially restored image at each iteration, and they are used to impose the degree of local smoothness on the solution. The resulting iterative algorithm exhibits increased convergence speed and better performance than typical regularized constrained least squares (RCLS) approach.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.8
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• pp.379-389
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• 2001

본 논문에서는 루프 반복들 간에 종속 관계가 존재하는 루프의 효율적 수행을 위한 새로운 루프 할당 기법을 제안한다. 그리고, 중앙 큐를 사용하여 공유 메모리 다중처리기에 루프 반복을 할당하는 기존 셀프 스케쥴링 기법들을 루프 캐리 종속성(loop-carried dependence)을 가진 루프의 할당에 적용하기 위해 제안한 기법을 이용한 그들의 변형에 대해 알아본다. 종속 거리를 고려하여 루프를 세 단계별로 할당하는 제안된 CDSS(Carried-Dependence Self-Scheduling) 기법 또한, 중앙 작업 큐를 기반으로 한 것이며 별도의 스케쥴러가 필요 없는 셀프 스케쥴링 알고리즘이다. 종속거리, 프로세서 수, 반복 수, 스케쥴링 연산 시간 등을 다양하게 하여 변형된 할당 기법들과 비교 분석한 결과, 제안한 기법은 양호한 부하 균형을 유지하였으며 변형된 다른 기법들에 비해 루프 수행 시간을 줄여 효율적임을 알 수 있었다. 다양한 실험 환경에서 평균적으로 제안한 CDSS, 변형된 SS, Factoring, GSS, CSS 기법 순으로 루프 수행 시간 측면에서 좋은 성능을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.1
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• pp.50-58
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• 2003

Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

• Journal of Korea Multimedia Society
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• v.4 no.3
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• pp.257-269
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• 2001

Because of increasing number of integrated circuit, there is many tries of making chip of neural network and some chip is exit. but this is not prefer because YLSI technology can't support so large hardware. So imitation of whole system of neural network is more prefer. There is common procedure in signal processing as in the neural network and pattern recognition. That is multiplication of large amount of signal and reading LUT. This is identical with some operation of MLP, and need iterative and large amount of calculation, so if we make this part with hardware, overall system's velocity will be improved. So in this paper, we design neutral network, not neuron which can be used to many other fields. We realize this part by following separated bits addition method, and it can be appled in the real time parallel process processing.

• Journal of Korea Game Society
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• v.9 no.2
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• pp.135-142
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• 2009

Mesh denoising is a method to remove noise applying various filters. However, those methods usually spend much time since filtering is performed on CPU. Because GPU is specialized for floating point operations and faster than CPU, real-time processing for complex operations is possible. Especially mesh denoising is adequate for GPU parallel processing since it repeats the same operations for vertices or triangles. In this paper, we propose mesh denoising algorithm based on bilateral filtering using GPU parallel processing to reduce processing time. It finds neighbor triangles of each vertex for applying bilateral filter, and computes its normal vector. Then it performs bilateral filtering to estimate new vertex position and to update its normal vector.