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http://dx.doi.org/10.9708/jksci.2010.15.2.009

CORDIC using Heterogeneous Adders for Better Delay, Area and Power Trade-offs  

Lee, Byeong-Seok (조선대학교 컴퓨터공학과)
Lee, Jeong-Gun (한림대학교 컴퓨터공학과)
Lee, Jeong-A (조선대학교 컴퓨터공학과)
Publication Information
Journal of the Korea Society of Computer and Information / v.15, no.2, 2010 , pp. 9-18 More about this Journal
Abstract
High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.
Keywords
CORDIC; Adder; Heterogeneous Adder;
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Times Cited By KSCI : 2  (Citation Analysis)
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