• Title/Summary/Keyword: 반복길이 부호화

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An analysis of optimal design conditions of LDPC decoder for IEEE 802.11n Wireless LAN Standard (IEEE 802.11n 무선랜 표준용 LDPC 복호기의 최적 설계조건 분석)

  • Jung, Sang-Hyeok;Na, Young-Heon;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.4
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    • pp.939-947
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    • 2010
  • The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

Design of Maritime Satellite Communication Systems Sharing Frequency with DVB-S2 (DVB-S2와 주파수 공유하는 해양 위성 통신 시스템 설계)

  • Ryu, Joon-Gyu;Oh, Deock-Gil;Yu, Heejung
    • Journal of Satellite, Information and Communications
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    • v.8 no.4
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    • pp.75-80
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    • 2013
  • In this paper, the Ka-band maritime satellite communication systems for mobile terminals are proposed. The design includes the link budget analysis, determination of modulation and coding schemes and the overall structure of a transmitter. To avoid the harmful effects on the existing DVB-S2 services, the proposed maritime satellite system using the same spectrum with DVB-S2 at the same time employs the very wideband spreading transmission. Additionally, omni-directional low-gain antennas should be equipped in a mobile terminal to reduce the system cost. These two considerations limit the maximum transmission rate of the proposed system. Due to the limitations, the proposed system includes 36 dB or 39 dB spreading gain depending on the modulation scheme and a link-adaptive repetition method depending on the level of rain attenuation. To support short packets with minimal performance loss, the turbo code used in 3GPP instead of LDPC(low density parity check code) is adopted. By combining them, the overall structure of low-rate maritime satellite communication system is designed.

Performance analysis of turbo codes based on underwater experimental data (수중 실험 데이터 기반 터보 부호 성능 분석)

  • Sung, Ha-Hyun;Jung, Ji-Won
    • Journal of Advanced Marine Engineering and Technology
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    • v.40 no.1
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    • pp.45-49
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    • 2016
  • The performance of underwater acoustic communication systems is sensitive to inter-symbol interference caused by delay spread developed from multipath signal propagation. The multipath nature of underwater channels causes signal distortion and error floor. In order to improve the performance, it is necessary to employ an iterative coding scheme. Of the various iterative coding schemes, turbo code and convolutional code based on the BCJR algorithm have recently dominated this application. In this study, the performance of iterative codes based on turbo equalizers with equivalent coding rates and similar code word lengths were analyzed. Underwater acoustic communication system experiments using these two coding techniques were conducted on Kyeong-chun Lake in Munkyeong City. The distance between the transmitter and receiver was 400 m, and the data transfer rate was 1 Kbps. The experimental results revealed that the performance of turbo codes is better for channeling than that of convolutional codes that use a BCJR decoding algorithm.

An analysis of BER performance of LDPC decoder for WiMAX (WiMAX용 LDPC 복호기의 비트오율 성능 분석)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.771-774
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    • 2010
  • In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

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An analysis of the effects of LLR approximation on LDPC decoder performance (LLR 근사화에 따른 LDPC 디코더의 성능 분석)

  • Na, Yeong-Heon;Jeong, Sang-Hyeok;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.405-409
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    • 2009
  • In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

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Efficient Coding of Motion Vector and Mode Information for H.264/AVC (H.264/AVC에서 효율적인 움직임 벡터와 모드 정보의 압축)

  • Lee, Dong-Shik;Kim, Young-Mo
    • Journal of Korea Multimedia Society
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    • v.11 no.10
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    • pp.1359-1365
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    • 2008
  • The portion of header in H.264 gets higher than those of previous standards instead of its better compression efficiency. Therefore, this paper proposes a new technique to compress the header of H.264. Unifying a sentence elementary in H.264, H.264 does not consider the distribution of element which be encoded and uses existing Exp-Golomb method, but it is uneffective for variable length coding. Most of the header are block type(s) and motion vector difference(s), and there are redundancies in the header of H.264. The redundancies in the header of H.264 which are analyzed in this paper are three. There are frequently appearing symbols and non-frequently appearing symbols in block types. And when mode 8 is selected in macroblock, all of four sub-macroblock types are transferred. At last, same values come in motion vector difference, especially '0.' This paper proposes the algorithm using type code and quadtree, and with them presents the redundant information of header in H.264. The type code indicates shape of the macroblock and the quadtree does the tree structured motion compensation. Experimental results show that proposed algorithm achieves lower total number of encoded bits over JM12.4 up to 32.51% bit reduction.

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Implementation of LDPC Decoder using High-speed Algorithms in Standard of Wireless LAN (무선 랜 규격에서의 고속 알고리즘을 이용한 LDPC 복호기 구현)

  • Kim, Chul-Seung;Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2783-2790
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    • 2010
  • In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

Efficient CAVLC Decoder VLSI Design for HD Images (HD급 영상을 효율적으로 복호하기 위한 CAVLC 복호화기 VLSI 설계)

  • Oh, Myung-Seok;Lee, Won-Jae;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.4 s.316
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    • pp.51-59
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    • 2007
  • In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

Turbo Coded OFDM Scheme for a High-Speed Power Line Communication (고속 전력선 통신을 위한 터보 부호화된 OFDM)

  • Kim, Jin-Young;Koo, Sung-Wan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.1
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    • pp.141-150
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    • 2010
  • In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is improved 3dB by increasing the number of iterations, 2 to 8, and interleaver length of a turbo encoder, 100 to 5000. The results in this paper can be applied to OFDM-based high-speed power line communication systems.

Data Compression Capable of Error Control Using Block-sorting and VF Arithmetic Code (블럭정렬과 VF형 산술부호에 의한 오류제어 기능을 갖는 데이터 압축)

  • Lee, Jin-Ho;Cho, Suk-Hee;Park, Ji-Hwan;Kang, Byong-Uk
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.5
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    • pp.677-690
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    • 1995
  • In this paper, we propose the high efficiency data compression capable of error control using block-sorting, move to front(MTF) and arithmetic code with variable length in to fixed out. First, the substring with is parsed into length N is shifted one by one symbol. The cyclic shifted rows are sorted in lexicographical order. Second, the MTF technique is applied to get the reference of locality in the sorted substring. Then the preprocessed sequence is coded using VF(variable to fixed) arithmetic code which can be limited the error propagation in one codeword. The key point is how to split the fixed length codeword in proportion to symbol probabilities in VF arithmetic code. We develop the new VF arithmetic coding that split completely the codeword set for arbitrary source alphabet. In addition to, an extended representation for symbol probability is designed by using recursive Gray conversion. The performance of proposed method is compared with other well-known source coding methods with respect to entropy, compression ratio and coding times.

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