• 한국산업보건학회지
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• 제25권2호
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• pp.202-210
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• 2015

Objectives: The purpose of this study was to examine clean room(C/R) structure, air conditioning and contamination control systems and to provide basic information for identifying a correlation between the semiconductor work environment and workers' disease. Methods: This study was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. The C/R structure and air conditioning method were investigated using basic engineering data from documentation for C/R construction. Furthermore, contamination parameters such as airborne particles, temperature, humidity, acids, ammonia, organic compounds, and vibration in the C/R were based on the International Technology Roadmap for Semiconductors(ITRS). The properties of contamination control systems and the current status of monitoring of various contaminants in the C/R were investigated. Results: 200 mm and 300 mm wafer fabrication facilities were divided into fab(C/R) and sub fab(Plenum), and fab, clean sub fab and facility sub fab, respectively. Fresh air(FA) is supplied in the plenum or clean sub fab by the outdoor air handling unit system which purifies outdoor air. FA supply or contaminated indoor air ventilation rates in the 200 mm and 300 mm wafer fabrication facilities are approximately 10-25%. Furthermore, semiconductor clean rooms strictly controlled airborne particles(${\leq}1,000{\sharp}/ft^3$), temperature($23{\pm}0.5^{\circ}C$), humidity($45{\pm}5%$), air velocity(0.4 m/s), air change(60-80 cycles/hr), vibration(${\leq}1cm/s^2$), and differential pressure(atmospheric pressure$+1.0-2.5mmH_2O$) through air handling and contamination control systems. In addition, acids, alkali and ozone are managed at less than internal criteria by chemical filters. Conclusions: Semiconductor clean rooms can be a pleasant environment for workers as well as semiconductor devices. However, based on the precautionary principle, it may be necessary to continuously improve semiconductor processes and the work environment.

• 한국통신학회논문지
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• 제34권8C호
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• pp.806-813
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• 2009

본 논문은 고속 무선 통신을 위한 모뎀 설계에 관한 것이다. 고속 통신을 위한 기술에는 여러 가지가 있는데, 그 중 넓은 주파수를 사용하고 여타 서비스에 주파수 간섭을 일으키지 않는 기술인 MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) 방식의 UWB (Ultra-Wideband) 모뎀의 SoC (System-on-Chip) 칩을 설계하였다. 개발된 모뎀 SoC 칩의 기저대역 시스템은 WiMedia에서 정의한 표준안을 따라서 설계되었다. 설계된 SoC 칩은 코어 부분인 FFT/lFFT (Fast Fourier Transform/lnverse Fast Fourier Transform), 송신부, 심볼동기 및 주파수 오프셋 추정부, 비터비 디코더, 그리고 기타 수신부등으로 구성되어 있다. 반도체 공정은 90nm CMOS (Complementary Metal-Oxide-Semiconductor) 공정을 사용하였고, 칩 사이즈는 약 5mm x 5mm 이다. 2009년 7월 20일에 fab-out되었다.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.98-102
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• 2021

GaOOH is obtained via hydrothermal synthesis procedure. The formed GaOOH is turned into α-Ga₂O₃ at 500℃ annealing. As the annealing temperatures increase the α-Ga₂O₃ is in part turned into β-Ga₂O₃ and fully turned into β-Ga₂O₃ after 1100℃. XPS and PL results reveal that heterojunction interface between α-Ga₂O₃ and β-Ga₂O₃ become maxim at 500℃ annealing condition, which result in the highest photocatalytic activity. The presence of heterojunction interface slows down the recombination process by separating photogenerated electron-hole pairs and thereby enhance the overall photocatalytic activity.

• 산업공학
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• 제22권1호
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• pp.73-84
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• 2009

In this paper, we propose a dispatching algorithm for constructing a Factory Operating System (FOS) which can operate semiconductor fabrication factories more efficiently and effectively. We first define ten dispatching criteria and propose two methods to apply the defined dispatching criteria sequentially and simultaneously (i.e. fixed dispatching architecture). However the fixed type methods cannot apply the criteria adaptively by considering changes in the semiconductor fabrication factories. To overcome this type of weakness, an adaptive dispatching architecture is proposed for applying the dispatching criteria dynamically based on the factory status. The status can be determined by combining evaluation results from the following three status criteria; target movement, workload balance, and utilization rate. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed adaptive dispatching architecture will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.

• 대한산업공학회지
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• 제41권3호
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• 산업경영시스템학회지
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• 제35권1호
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• pp.79-86
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• 2012

This study focuses on the problem of scheduling wafer lots of several recipe(operation condition) types in the photolithography workstation in a semiconductor wafer fabrication facility, and sequence-dependent recipe set up times may be required at the photolithography machines. In addition, a lot is able to be operated at a machine when the reticle(mask) corresponding to the recipe type is set up in the photolithography machine. We suggest various heuristic algorithms, in which developed recipe selection rules and lot selection rules are used to generate reasonable schedules to minimizing the total weighted flowtime. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the total weighted flowtime of the wafer lots with ready times.

• 산업공학
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• 제21권2호
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• pp.141-150
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• 2008

In this paper, an efficient control method for semiconductor fabrication process is presented. Generally, control is performed with data which is under the influence of process disturbance. EWMA is one of the most popular control methods in semiconductor fabrication that effectively deals with varying process condition. A new method using EWMA, called the Dual Damping EWMA, is presented in this study to reduce over-control by separating weight factor of input and output. The goal is to reflect Drift but reduce the effects of White noise in run to run control. Simulation is performed to evaluate the performance of DPEWMA and to compare with EWMA and Double EWMA.

• 한국화재소방학회논문지
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• 제26권5호
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• pp.41-47
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• 2012

첨단산업기술인 반도체, LCD 등 제조의 핵심공정인 클린룸은 생산제품의 성능 및 품질에 절대적인 영향을 미치는 가장 중요한 공정이다. 그러나 국내는 방화공학적인 측면에서 과학적이고 종합안전대책에 대한 체계적인 연구가 제대로 이루어지지 않고 있다. 본 연구는 LCD 제조공정 클린룸에 설치하는 제연시스템의 성능 및 문제점을 파악하여 이에 대한 개선방안을 도출하기 위하여 여러 시나리오를 고려한 화재시뮬레이션과 피난시뮬레이션을 통하여 분석하였다. LCD 제조공정의 클린룸 화재 및 연기확산에 대하여 분석한 결과 화재시 공조기의 연동정지는 반드시 필요하며 연기의 부력을 고려하여 FAB 상부에 배연을 할 수 있도록 하여야 한다. 또한 대규모 클린룸의 경우 화재특성상 스프링클러헤드의 집열 성능이 떨어지므로, 조기반응형 헤드의 설치 및 작동시간을 빠르게 하기 위한 보조장치를 설치하여야 한다. 특히, 대공간 클린룸은 자동화 공정으로 거주밀도가 낮지만, 복잡한 생산장비의 배치와 방진복을 착용하고 근무해야하는 환경특성 때문에 화재시 피난안전성능 확보가 어렵기 때문에 공정 내 위험요소의 철저한 관리 및 주기적인 교육과 훈련이 필요하며, 방재선진국의 기준에 준하는 수준의 국내 관련기술 기준을 정립할 필요가 있다.

• 대한산업공학회지
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• 제36권2호
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• 마이크로전자및패키징학회지
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• 제31권3호
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• pp.24-37
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• 2024

반도체 패키지의 초박형화로 인해 작은 열하중에서도 Warpage가 크게 발생하며, 이는 제품 신뢰성에 심각한 영향을 미칠 수 있다. 특히 몰드 경화 공정에서의 Warpage 예측은 복합적인 열-화학-기계적 현상으로 인해 어려운 문제이다. 본 연구는 몰드 경화 공정에서 Warpage를 예측하기 위한 비용 절감형 머신러닝 모델 구축 방법을 분석하였다. 경화 공정에서 시간과 온도에 따른 경화도를 특성화하고, 이를 통해 재료의 기계적 특성을 수치화하였다. ABAQUS UMAT을 사용해 특성화된 재료 특성으로 FEM 시뮬레이션 모델을 개발하였으며, 패키지의 적층 구조에 따른 Local Warpage를 예측하는 Warpage formula를 제안하고 FEM 시뮬레이션 결과와 비교하여 검증하였다. 개발된 모델과 이론식을 통해 다양한 설계 인자를 고려한 몰드 경화 공정에서 Warpage를 저비용으로 예측할 수 있는 방법을 제시하였다. 이 방법은 머신러닝 입력 변수로 Warpage formula를 사용하고, 훈련 데이터 세트를 효율적으로 구축하여 Single IC 패키지 기준으로 98% 이상의 예측 정확도와 96.5%의 시뮬레이션 시간 절약을 가능하게 한다.