• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.923-928
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• 1986

This paper describes the design and fabrication of a high performance digital tuning analog component integrated circuit that contains a television station detector and decoders(H and L types). When the comparator level sampling method is used, this integrated circuit can be used as a stable channel selector for an external circuit with very large signal variation. It has been fabricated using the SST bipolar standard process and its chip size is 2.2x2.1mm\ulcorner As a result, we have succeeded in fabricating the IC that satisfies the D.C characteristics, and the channel station detector and decoder function.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.53-60
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• 2009

Due to increased integration density and reduced threshold voltages, leakage current reduction becomes important in the semiconductor IC design for low power consumption. In a combinational logic circuit, the leakage current in the standby state depends on the values of the input. In this research, we developed a new input vector control method to minimize the leakage power. A new efficient algorithm is developed to find the minimal leakage vector. It can reduce the leakage current by 15.7% from the average leakage current and by 6.7% from the results of simulated evolution method during standby or idle states for a set of benchmark circuits. The minimal leakage input vector, with idle input signal, can also reduce the leakage current by 6.8% from the average leakage current and by 3.2% from the results of simulated evolution method for sequential circuits.

• Proceedings of the Optical Society of Korea Conference
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• 2000.08a
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• pp.22-23
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• 2000

GaAs/AlGaAs나 InGaAs/InGaAsP와 같은 반도체 기판을 이용한 전계광학 광변조기는 LD나 SOA와 같은 광소자와 단일기판 집적이 가능하고 낮은 chirping과 높은 변조대역폭을 갖는 외부광변조기로서의 장점으로 인하여 마이크로파 대역의 초고속광통신소자로 각광을 받아왔다. 특히 진행파의 속도가 정합된 traveling-wave 전극 구조를 갖는 경우 변조대역폭은 30-400Hz에 달하고 있다$^{(1)}$ . 그러나 한편으로는 반도체의 전계광학계수(electro-Optic Coefficient)가 LiNbO$_3$에 비해 10분의 1정도로 작아 상대적으로 동작전압이 커지는 단점이 대두되며 실제 구동전압이 수십 V에 이르고 있다. 이런 단점을 극복하기 위하여 p-i-n 구조를 이용하여 전계 집속도를 높이는 방법이 제안되어 동작전압이 2 V/mm 정도까지 감소하였다$^{(2)}$ . 본 논문에서는 이와 같은 반도체 전계광학 광변조기에서의 소신호 및 대신호 광변조특성을 분석함으로써 보다 높은 변조대역폭과 보다 낮은 동작전압을 갖는 구조를 연구하였다. (중략)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• Korean Journal of Optics and Photonics
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• v.14 no.4
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• pp.454-459
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• 2003

We report the first demonstration of 10 Gb/s wavelength conversion in a Mach-Zehnder interferometric wavelength converter monolithically integrated with a loss-coupled DFB probe source. The integrated device is fabricated using a BRS (buried ridge stripe) structure with an undoped InP clad layer on the top of a passive waveguide to reduce high propagation loss. The device exhibited a static extinction ratio of 11 dB. Good performance at 10 Gb/s is obtained with an extinction ratio of 7 dB and a power penalty of 2.8 dB at a 10$^{-9}$ bit error rate.

• Journal of the Korean Society for Railway
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• v.15 no.2
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• pp.116-121
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• 2012

DC/DC switching power converters produce DC output voltages from different DC input sources. The converter is used in regenerative braking of DC motors to return energy back in the supply, resulting in energy savings for the systems containing frequent stops. The DC/DC converter is composed of a PWM-IC (pulse width modulation integrated circuit) controller, a MOSFET (metal-oxide semi-conductor field-effect transistor), an inductor, capacitors, and resistors, etc. PWM is applied to control and regulate the total output voltage. In this paper, radiation shows the main influence on the changes in the electrical characteristics of comparator, operational amplifier, etc. in PWM-IC. In the PWM-IC operation, the missing pulses, the changes in pulse width, and the changes of the output waveform are studied by the simulation program with integrated circuit emphasis (SPICE) and compared with experiments.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.340-346
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• 2000

Traveling wave type semiconductor optical amplifiers integrated with spot-size-converter (SSC-TW-SOA) have been extensively studied for the improvement of coupling effiClency With single-mode fiber and fO! the cost reducClon 111 a packaging In tlIis paper the slructural dependence of the spot-slZe-converter on the effective facet reflectlvllY $R_{eff}$ was experimentally as well as thcoretienlly mvestlgated. It was shown that not only a sufficient mode-conversion in a sse region along the latersl and tran~verse directions but also an introductIOn of angled-facet were very essential in order to reduce $R_{eff}$ Very small ripple less than 0.1 dB in an amplified spontaneous emission spectrum was observed with the fabncated SSC-lW-SOA which consists of the wrndow length of $20\mu\textrm{m}$, facet angle of $7^{\circ}$, and antlrelleetioll-coated facet of ] % reflectivity.tivity.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.396-399
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• 2002

Using a bi-layer anti-reflection coating of $TiO_2$and $SiO_2,$ we have achieved a minimum facet reflectivity of $~10^{-5}$ and a band width of 27 nm for a reflectivity of $~10^{-4}$ or less for 1.3 $\mu\textrm{m}$ spot size converter integrated semiconductor lasers. This coating is applicable to external-cavity-tuned laser sources and semiconductor optical amplifiers.

• Journal of IKEEE
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• v.23 no.3
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• pp.988-993
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• 2019

Over the past decades, the semiconductor industry has continuously scaled down the size of semiconductor devices to increase those performance and to integrate them at higher density on the chip. However, facing the reduction of gate control, higher leakage current, and short channel effect, there is a growing interest in next-generation semiconductors which can overcome these problems. In this paper, we discuss digital circuit design techniques using CNTFET(Carbon NanuTube Field Effect Transistor), which are attracting attention as candidates for the next generation of semiconductors. Since the structure of CNTFETs are clearly different from the structure of the structure of conventional MOSFETs, we will discuss how to utilize existing digital circuit methodology when designing digital circuits using the CNTFETs, and then simulate the performance differences between the two devices.