• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.4
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• pp.7-16
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• 1971

A negative resistance element in the form of current control can be obtained by using a pair transistor circuit. This negative resistance element can be used in the generation of square pulse, and also in the realization of pulse width modulation circuit by superposing signal current on its bias current. The each bias current of pair circuit increases alternatively according to the polarity of the input signal. In order to satisfy this condition, a modified full wave rectification circuit has been adopted for supplying the input signal. Theoritical analysis of pulse times and design guidances for practical modulation circuit parameters are presented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.1-6
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• 2009

The experimental results of exposing IGBT (Insulated Gate Bipolar Transistor) samples to gamma radiation source show shifting of threshold voltages in the MOSFET and degradation of carrier mobility and current gains. At low total dose rate, the shift of threshold voltage is the major contribution of current increases, but for more than some total dose, the current is increased because of the current gain degradation occurred in the vertical PNP at the output of the IGBTs. In the paper, the collector current characteristics as a function of gate emitter voltage (VGE) curves are tested and analyzed with the model considering the radiation damage on the devices for gate bias and different dose. In addition, the model parameters between simulations and experiments are found and studied.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1420-1421
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• 2011

비정질 IGZO 박막 트랜지스터에 포지티브 직류/교류 게이트 바이어스를 인가하여 신뢰성을 분석하고 비정질 IGZO 박막 트랜지스터의 신뢰성을 고려한 시프트 레지스터 회로를 설계하였다. 비정질 IGZO 박막 트랜지스터의 문턱전압은 바이어스 스트레스가 인가되었을 때 양의 방향으로 이동하였고, 전류가 감소하였다. 또한 문턱전압은 직류 바이어스 스트레스가 인가되었을 때 교류 바이어스 스트레스가 인가 되었을 때 보다 더 양의 방향으로 이동하였다. 총 8개의 박막 트랜지스터로 구성된 일반적인 시프트 레지스터 회로에서는 특정 박막 트랜지스터에 직류 바이어스 스트레스가 걸리기 때문에 비정질 IGZO 박막 트랜지스터를 이용하여 구동할 때 회로 오동작을 유발할 수 있다. 비정질 IGZO 박막 트랜지스터의 신뢰성 결과를 고려하여 총 9개의 박막 트랜지스터로 구성된 교류 동작하는 시프트 레지스터 회로를 설계하였다. 모든 소자에 직류 바이어스 스트레스가 걸리지 않도록 회로를 설계하였으며, 추가된 트랜지스터의 채널 너비가 매우 작기 때문에 트랜지스터가 하나 추가되어도 회로가 차지하는 면적에는 거의 변화가 없다. 바이어스 스트레스에 따른 소자 열화를 고려하여 시뮬레이션을 해 본 결과 일반적인 회로에서는 회로 오동작이 관측된 반면, 제안한 회로에서는 문제없이 동작하는 것을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.13-18
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• 1999

The trap density by the stress bias in silicon oxides with different thicknesses has been investigated. The trap density by stress bias was shown to be composed of on time current and off time current. The on time trap density was composed of dc current. The off time trap density was caused by the tunneling charging and discharging of the trap in the interfaces. The on time trap density was used to estimate to the limitations on oxide thicknesses. The off time trap density was used to estimate the data retention in nonvolatile memory devices.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.11
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• pp.36-43
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• 2015

A pixel-level readout circuit is studied for 2-dimensional microbolometer focal plane arrays (FPAs). A current mirroring injection (CMI) input circuit with 2-step current-mode bias suppression is proposed for a pixel-level architecture with high responsivity and long integration time. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a $320{\times}240$ microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed 2-step bias-current suppression has sufficiently low calibration error with wide calibration range, and the calibration range and error can be easily optimized by controlling some design parameters. Due to high responsivity and a long integration time of more than 1 ms, the noise equivalent temperature difference (NETD) of the proposed circuit can be improved to 26 mK, which is much better than that of the conventional circuits, 67 mK.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.25-34
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• 2002

In this paper, silicidation induced Schottky contact area was obtained using the current voltage(I-V) characteristics of shallow cobalt silicided p+-n and n+-p junctions. In reverse bias region, Poole-Frenkel barrier lowering influenced predominantly the reverse leakage current, masking thereby the effect of Schottky contact formation. However, Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n+-p junction in the forward bias region. The increase of leakage current in silicided n+-p diodes is consistent with the formation of Schottky contact via cobalt slicide penetrating into the p-substrate or near to the junction area and generating trap sites. The increase of reverse leakage current is proven to be attributed to the penetration of silicide into depletion region in case of the perimeter intensive n+-p junction. In case of the area intensive n+-p junction, the silicide penetrated near to the depletion region. There is no formation of Schottky contact in case of the p+-n junction where no increase in the leakage current is monitored. The Schottky contact amounting to less than 0.01% of the total junction was extracted by simultaneous characterization of forward and reverse characteristics of silicided n+-p diode.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.285-291
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• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.227-228
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• 2015

본 논문에서는 Optocoupler 절연형 오프라인 플라이백 변환기 궤환 단의 직류 바이어스 해석 기법을 제안한다. 직류 바이어스 해석을 통해 목표한 Current Transfer Ratio(CTR)를 얻고 Junction Capacitance($C_j$)를 측정하여 제어기 설계에 적용시켜 안정도 및 성능을 측정하였다. NCP1230, PC817, TL431 IC를 이용하여 플라이백 변환기의 제어회로를 제작하였고, 시뮬레이션을 이용해 직류 바이어스 해석 기법의 타당성을 검증하였다.

• Journal of Navigation and Port Research
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• v.27 no.1
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• pp.81-86
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• 2003

In the paper, the power amplifier using active biasing for LDMOS MRF-21060 is designed and fabricated. Driving amplifier using AH1 and parallel power amplifier AH11 is made to drive the LDMOS MRF 21060 power amplifier. The variation of current consumption in the fabricated 5 Watt power amplifier has an excellent characteristics of less than 0.1A, whereas passive biasing circuit dissipate more than 0.5A. The implemented power amplifier has the gain over 12 dB, the gain flatness of less than $\pm$0.09dB and input and output return loss of less than -19dB over the frequency range 2.11~2.17GHz. The DC operation point of this power amplifier at temperature variation from $0^{\circ}C$ to $60^{\circ}C$ is fixed by active circuit.