• Title/Summary/Keyword: 몽고인

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Hardware Implementation of Optical Fault Injection Attack-resistant Montgomery exponentiation-based RSA (광학 오류 주입 공격에 강인한 몽고메리 지수승 기반 RSA 하드웨어 구현)

  • Lee, Dong-Geon;Choi, Yong-Je;Choi, Doo-Ho;Kim, Minho;Kim, Howon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.76-89
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    • 2013
  • In this paper, we propose a novel optical fault detection scheme for RSA hardware based on Montgomery exponentiation, which can effectively detect optical fault injection during the exponent calculation. To protect the RSA hardware from the optical fault injection attack, we implemented integrity check logic for memory and optical fault detection logic for Montgomery-based multiplier. The proposed scheme is considered to be safe from various type of attack and it can be implemented with no additional operation time and small area overhead which is less than 3%.

A Study of the Modulus Multiplier Design for Speed up Throughput in the Public-key Cryptosystem (공개키 암호시스템의 처리속도향상을 위한 모듈러 승산기 설계에 관한 연구)

  • 이선근;김환용
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.4
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    • pp.51-57
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    • 2003
  • The development of the communication network and the other network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, we proposed M3 algorithm for the reduced processing time in the montgomery multiplication part. Proposed M3 algorithm using the matrix function M(.) and lookup table perform optionally montgomery multiplication with repeated operation. In this result, modified repeated operation part produce 30% processing rate than existed montgomery multiplicator. The proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

New Multiplier using Montgomery Algorithm over Finite Fields (유한필드상에서 몽고메리 알고리즘을 이용한 곱셈기 설계)

  • 하경주;이창순
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 2002.06a
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    • pp.190-194
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    • 2002
  • Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.

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A New Modular Arithmetic Algorithm and its Hardware Structure for RSA Cryptography System (RSA 암호 시스템의 고속 처리를 위한 새로운 모듈로 연산 알로리즘 및 하드웨어 구조)

  • 정용진
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10a
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    • pp.646-648
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    • 1999
  • 본 논문에서는 RSA 암호 알고리즘의 핵심 계산 과정인 모듈로 곱셈 연산의 효율적인 하드웨어 구현을 위해 새로운 알고리즘과 하드웨어 구조를 제시한다. 기존의 몽고메리 알고리즘이 LSB 우선 방법을 사용한 것과는 달리 여기서는 MSB 우선 방법을 사용하였으며, RSA 암호 시스템에서 키가 일정 기간 동안 변하지 않고 유지된다는 점에 착안해 계수(Modulus)에 대한 보수(Complements)를 미리 계산해 놓고 이를 이용하여 모듈로 감소 처리를 간단히 덧셈으로 치환하도록 하였다. 보수들을 저장할 몇 개의 레지스터와 그들 중 하나를 선택하기 위한 간단한 멀티플렉서(Multiplexer)만을 추가함으로써 몽고메리 알고리즘이 안고 있는 홀수 계수 조건과 사후 연산이라는 번거로움을 없앨 수 있다. 본 논문에서 제안하는 알고리즘은 하드웨어 복잡도가 몽고메리 알고리즘과 비슷하며 그 내부 계산 구조를 보여주는 DG(Dependence Graph)의 지역 연결성 (Local Connection), 모듈성(Modularity), 데이터의 규칙적 종속성 (Regular Data Dependency)등으로 인한 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

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A Design of Efficient Modular Multiplication based on Montgomery Algorithm (효율적인 몽고메리 모듈러 곱셈기의 설계)

  • Park, Hye-Young;Yoo, Kee-Young
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.1003-1006
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    • 2004
  • 본 논문에서는 몽고메리 모듈러 곱셈(Montgomery Modular Multiplication) 알고리즘을 이용하여 효율적인 모듈러 곱셈기를 제안한다. 본 논문에서 제안한 곱셈기는 프로그램 가능한 셀룰라 오토마타(Programmable Cellular Automata, PCA)를 기반의 구조로 설계되어 하드웨어 복잡도를 줄이고, 곱셈시 몽고메리 알고리즘을 이용하여 일반적인 나눗셈 없이 모듈러 연산을 수행하여 시간 복잡도를 최소화 한다. 제안된 곱셈기는 시간적, 공간적인 면에서 간단하고 효과적으로 구성되어 지수연산을 위한 하드웨어의 하부구조나 오류 수정 코드(Error Correcting Code)의 연산에서 효율적으로 이용될 수 있을 것이다.

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Crisis Construction in the Inner Mongolia Grassland and the Controversy of Desertification: The Emergence of Grassland Chicken Farming (중국 내몽고 초원의 위기와 사막화 논쟁 -초원목계(草原牧鷄)가 등장하기까지-)

  • Lee, Seonhwa
    • Journal of the Korean Geographical Society
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    • v.47 no.6
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    • pp.836-852
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    • 2012
  • Based on a long-term ethnographic study, this paper examines how the propositions and practices for desertification management in Inner Mongolia, China have changed over time. Desertification as an ecological issue cannot simply be treated as a something "natural" or "social," while it is an outcome of the construction made by both human and non-human agents. My research has found that the propositions for desertification management have been involved in the process of defining desertification, particularly by selecting different actors related to the ecological process in this region. Ultimately, the crisis in the inner Mongolia has always been constructed by the ways in which the selected actors and their relationships are differently defined. My study also reveals that although the proposed preventive measures, including afforestation, area protection, and pasturing prohibition, have tried to reconcile the conflicts of interest among the different actors, they have always been faced with certain limitations and failed in dryland management. In this historical context of crisis construction, by introducing a new non-human agent, "the chicken," the project of grassland chicken farming has eventually appeared to be an innovative strategy that can overcome the earlier limitations and coordinate the interests of Mongolian pastoralists who have suffered from economic difficulty.

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Design of an Optimal RSA Crypto-processor for Embedded Systems (내장형 시스템을 위한 최적화된 RSA 암호화 프로세서 설계)

  • 허석원;김문경;이용석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.4A
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    • pp.447-457
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    • 2004
  • This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

Design of high-speed RSA processor based on radix-4 Montgomery multiplier (래딕스-4 몽고메리 곱셈기 기반의 고속 RSA 연산기 설계)

  • Koo, Bon-Seok;Ryu, Gwon-Ho;Chang, Tae-Joo;Lee, Sang-Jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.17 no.6
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    • pp.29-39
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    • 2007
  • RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.