• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.95-105
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• 2002

This paper describes an efficient method to implement a hardware circuit of RSA public key cryptographic algorithm, which is important to public-key cryptographic system for an authentication, a key exchange and a digital signature. The RSA algorithm needs a modular exponential for its cryptographic operation, and the modular exponential operation is consists of repeated modular multiplication. In a numerous algorithm to compute a modular multiplication, the Montgomery algorithm is one of the most widely used algorithms for its conspicuous efficiency on hardware implementation. Over the past a few decades a considerable number of studies have been conducted on the efficient hardware design of modular multiplication for RSA cryptographic system. But many of those studies focused on the decrease of operating time for its higher performance. The most important thing to design a hardware circuit, which has a limit on a circuit area, is a trade off between a small circuit area and a feasible operating time. For these reasons, we modified the Montgomery algorithm for its efficient hardware structure for a system having a limit in its circuit area and implemented the refined algorithm in the IESA system developed for ETRI's smart card emulating system.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.33-35
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• 2000

본 논문에서는 몽고메리 알고리즘과 LR 이진 제곱 곱셈 알고리즘을 사용하여 n 비트 메시지 블록에 대해 모듈러 지수 연산을 수행하는 지수 연산 프로세서를 설계한다. 이 프로세서는 제어장치, 입출력 시프트 레지스터, 시주 연산 장치 등 3개의 영역으로 나누어진다. 설계된 지수 연산 프로세서의 동작을 검증하기 위해 VHDL를 사용하여 모델링하고 MAX+PLUS II를 사용하여 시뮬레이션 한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.217-223
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• 2009

Recently, the development of the various network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.4
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• pp.223-230
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• 2006

The method of implementing a modular multiplier for Montgomery multiplication by using an adder depends on a selected adder. When using a CPA, there is a carry propagation problem. When using a CSA, it needs an additional calculation for a final result. The Multiplier using a Multi-precision CSA can solve both problems simultaneously by combining a CSA and a CPA. This paper presents an improved MP-CSA which reduces hardware resources and operation time by changing a MP-CSA's carry chain structure. Consequently, the proposed multiplier is more suitable for the module of long bit multiplication and exponentiation using a modular multiplier repeatedly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.57-66
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• 2004

This paper proposes the design of a 2,048-bit RSA based on RNS(residue number systems) Montgomery modular multiplier As the systems that RNS processes a fast parallel modular multiplication for a large word partitioned into small words, we introduce Montgomery reduction method(MRM)［1］based on Wallace tree modular multiplier and 33 RNS bases with 64-bit size for RNS Montgomery modular multiplication in this paper. Also, for fast RNS modular multiplication, a modified method based on Chinese remainder theorem(CRT)［2］ is presented. We have verified 2,048-bit RSA based on RNS using Samsung 0.35${\mu}{\textrm}{m}$ technology and the 2,048-bit RSA is performed in 2.54㎳ at 100MHz.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.84-90
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• 2001

The development of network and the other communication-network can generate serious problems. So, it is highly required to control security of network. These problems related secu be developed and keep up to confront with anti-security part such as hacking, cracking. Th way to preserve security from hacker or cracker without developing new cryptographic algori keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplicator for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplicator enforce the real time processing and prevent outer cracking.

• Journal of the Korea Society of Computer and Information
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• v.28 no.2
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• pp.69-75
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• 2023

Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.243-252
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• 2023

As an efficient key recovery attack on SIDH/SIKE was proposed, CSIDH is drawing attention again. CSIDH is an isogeny-based key exchange algorithm that is safe against known attacks to date, and provide efficient NIKE by modernizing CRS scheme. In this paper, we firstly present the optimized implementation of CSIDH-512 on ARM Cortex-M7. We use three-level hybrid Montgomery reduction and present the results of our implementation, limitations, and future research directions. This is a CSIDH implementation in 32-bit embedded devices that has not been previously presented, and it is expected that the results of this paper will be available to implement CSIDH and derived cryptographic algorithms in various embedded environments in the future.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.