• Title/Summary/Keyword: 모드 선택기

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AIGaInAs Seletive Area Growth using MOCVD for Spot Size Converter Laser Diode (Spot Size Converter 레이저 다이오드 제작을 위한 AIGaInAs 선택적 영역 성장)

  • 방영철;김현수;김준연;이은화;이중기;김태진;박성수;황선령;강중구
    • Proceedings of the Optical Society of Korea Conference
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    • 2003.07a
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    • pp.92-93
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    • 2003
  • 초고속 광전송 네트워크에 사용되는 광부품으로 단일 모드 광섬유와의 낮은 광 결합 손실을 가지는 레이저 다이오드 개발이 필수적이다. 이러한 레이저 다이오드의 요구되는 특성으로써 저가의 광부품 제작을 위해 thermoelectric cooler 없이 고온에서 안정된 동작을 하는 uncooled type에, 광 isolator 도움없이 광반사에 의한 광손실을 줄여야 한다. 이러한 요건을 충족시키기 위하여 선택적 영역 MOCVD성장을 이용한 InP/InGaAsP 계열의 SSC-LD(spot-size converter integrated LD)를 연구하여 왔다. (중략)

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A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

An analysis of link margin for MB-OFDM UWB system in multi-path channel (다중 경로 채널에서의 MB-OFDM UWB 시스템 링크 마진 분석)

  • Shin, Cheol-Ho;Choi, Sang-Sung;Pack, Jeong-Ki
    • The KIPS Transactions:PartC
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    • v.13C no.6 s.109
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    • pp.677-684
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    • 2006
  • This paper investigates the link margin of MB-OFDM UWB system quantitatively. Various simulations are performed considering the implementation loss by imperfect synchronization unit and the effect of multi-path fading channels. MB-OFDM UWB system uses ZP(Zero Padding) instead of CP(Cyclic Prefix) and supports two transmission modes; one is TFI(Time Frequency Interleaving) mode that transmits OFDM symbols using different carrier frequency from symbol to symbol according to Time Frequency(TF) codes, the other is FFI(Fixed Frequency Interleaving) mode that transmits OFDM symbols using a specific carrier frequency. The advantage of if and TFI is to be able to increase the transmitting power effectively compared to the existed OFDM systems that transmit the signal continuously at the same average transmitting power. From the analysis results of Ink margin, to guarantee the service range of 4m in 200Mbps mode, TFI mode must necessarily be implemented and the service range of 480Mbps mode is estimated about 1-2m in the line-of-sight multi-path channel (CMI).

A Design of Parameterized Viterbi Decoder for Multi-standard Applications (다중 표준용 파라미터화된 비터비 복호기 IP 설계)

  • Park, Sang-Deok;Jeon, Heung-Woo;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.6
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    • pp.1056-1063
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    • 2008
  • This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

Design of a Interdigital Microstrip Bandpass Filter (깍지낀 마이크로스트립 대역통과 여파기 설계)

  • 신진옥;전성근;이문수
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.3
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    • pp.565-573
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    • 2000
  • In this paper, a interdigital microstrip bandpass filter is designed. A interdigital microstrip bandpass filter has many advantages such as insertion return loss, lower return loss, higher frequency selectivity and smaller in size in comparison with the conventional coupled line filter. A interdigital microstrip bandpass filter consists of quasi TEM-mode strip line resonators between parallel ground plant. Each resonator element is a quarter wavelength long of the center frequency and is short circuited at one end and open circuited at the other end. In the filter design, Ensemble software is used. Experimental results show that the bandwidth of interdigital microstrip bandpass filter is 2.52GHz, insertion loss is -1.8dB and return loss is -17.0dB at 11.20Hz.

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Power system Design of KITSAT-4 Satellite (과학위성 1호 전력계 설계)

  • 김일송;이준영;윤명중
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.5
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    • pp.475-483
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    • 2000
  • This paper describes designs about the power system of KITSAT-4 satellite. The KITSAT-4 power system is mainly composed of power stage and control stage. The power stage is a 200〔W〕 buck converter and control stages are hardware controller and software controller The hardware controller is PPT(Peak Power Tracker), battery voltage controller and software controller is battery current controller and direct duty controller. So the operation of power system has many advantages in that it can select controller according to reliable control and precise control. The controller design methods are presented and the small signal analyses are performed to verify system stability.

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The design for controllabel self-checking checker (제어 가능한 자체검사 특성 검사기 설계)

  • 양성현;이기서
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.5
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    • pp.1149-1159
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    • 1998
  • This paper presents the Controllable Self-Checking(CSC) Checker at which can be used the Fault-Tolerant System with the redundancy. According to the critical level of output(of system), especially, it can be instructed the time if it has to check the output or not. We adop the deterministic test, performed on-line, to detect the faults with a minimal test set. The results show the Parity 2-rail checker(P-TRC) which is designed much simpler than the checker has the higher fault coverage than the existent checker.

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Measurement of Behaviors of Optical Filter using Evanescent Field Coupling between Single Mode Fiber and Multimode Planar Waveguide (단일모드 광섬유와 다중모드 평면도파로의 소산장결합을 이용한 광필터의 동작특성 측정)

  • Kim, Kwang-Taek;Yu, Ho-Jong;Song, Jae-Won;Kim, Si-Hong;Kang, Shin-Won
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.7
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    • pp.42-49
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    • 1999
  • In this paper, we proposed a simple measurement method to find the behaviors of the fiber-to-waveguide coupler. The polished fiber blocks and planar waveguides on silicon dioxide were fabricated independently and then optically coupled by physical pressure. Several kinds of polymer with different refractive indices were used for waveguide films. The proposed method makes it possible to measure the center wavelength, bandwidth, extinction ratio, and polarization dependence of the coupler during fabrication procedure. The wavelength sensitivity increased with refractive index of polymer. The symmetric planar waveguide structure and isotropic property of guiding materials reduced polarization dependent property. Insertion loss of the coupler was less than 0.5dB. It is expected that our measurement method is useful for developing various optical devices using evanescent coupling between polished fiber and planar waveguide such as optical modulators and filters etc.

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Application of Turbo Code for Digital Audio Broadcasting (DAB) System (디지털 오디오 방송을 위한 터보부호의 응용)

  • 김한종
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.2
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    • pp.176-187
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    • 2002
  • The digital Audio Broadcasting (DAB) system adopts Coded OFDM(COFDM) for channel coding. The COFDM is a combined technique of multicarrier transmission(OFDM) and punctured convolutional coding with viterbi error correction. Because the channel coding is an important topic for OFDM systems, this paper proposes a new turbo coded OFDM system that replaces the existing RCPC codec by a turbo codec without modifying the puncturing procedure and puncturing vectors defined in the standard DAB system for compatibility. The performance of a new system is compared to that of the conventional system under the frequency selective Rician fading channel and the frequency selective Rayleigh fading channel in conjunction with DAB transmission mode I suitable for the terrestrial single frequency network(SFN) broadcasting. The standard system's performance was improved with the aid of turbo codec.

A Design of Parameterized Viterbi Decoder using Hardware Sharing (하드웨어 공유를 이용한 파라미터화된 비터비 복호기 설계)

  • Park, Sang-Deok;Jeon, Heung-Woo;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.93-96
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    • 2008
  • This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

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