• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.39 no.3
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• pp.218-229
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• 2003

A new biotelemetry method that the installation and the treatment of equipment is convenient and the instantaneously detailed location of the fish attached the pinger is able to track comparatively easily was developed. The receiving system in this biotelemetry method was advanced for track the detailed behavior of the fish by the miniature tracking pinger, because it was a burden to fish to add the pinger with the water temperature and the pressure sensor. By combining of the super short base line (SSBL) method to detect the direction of pinger and the pinger synchronizing method to measure the range from receiving transducer to pinger, the three dimensional locations of fish to the receiving transducer is gotten instantaneously. The receiving system is devised to realize the high precision or wide detection range by application of the basic design method for receiving system of biotelemetry developed by the present authors and the hydrophone array configuration. The measurement distance error in the pinger synchronizing method is minimized through the correction of which the deviation of transmission pluse period of pinger is caused by changing water temperature. A prototype system which is able to track the instantaneously detailed location of the fish by the SSBL and pinger synchronizing biotelemetry (SPB) method was produced.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.1
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• pp.36-41
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• 2018

This paper presents an implementation of a millimeter-wave(W band) multiflare-angle horn antenna. The proposed antenna is a multimode dual-polarized square horn having equal E- and H-plane beamwidths and consists of a multimode generating section, a four-square-waveguide exciter, orthomode transducers, and power combiners for the sum pattern formation. The antenna structure has been designed to allow for easy fabrication and the designed antenna has been fabricated to a precision of ${\pm}0.02mm$ by layer-by-layer machining and diffusion bonding. The input reflection coefficient and the radiation pattern of the fabricated antenna have been measured using a network analyzer and a far-field test facility. Measurements show that the proposed antenna has 17.7~18.3 dBi gain, $25.2{\sim}28.5^{\circ}$ beamwidth, and an input VSWR between 1.02~1.75, within ${\pm}0.5GHz$ from the center frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.432-443
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• 2017

The primary goal of the MPEG-H 3D Audio standard is to provide immersive audio environments for high-resolution broadcasting services such as UHDTV. This standard incorporates a wide range of technologies such as encoding/decoding technology for multi-channel/object/scene-based signal, rendering technology for providing 3D audio in various playback environments, and post-processing technology. The reference software decoder of this standard is a structure combining several modules and can operate in various modes. Each module is composed of independent executable files and executed sequentially, real time decoding is impossible. In this paper, we make DLL library of the core decoder, format converter, object renderer, and binaural renderer of the standard and integrate them to enable frame-based decoding. In addition, by measuring the computation complexity of each mode of the MPEG-H 3D-Audio decoder, this paper also provides a reference for selecting the appropriate decoding mode for various hardware platforms. As a result of the computational complexity measurement, the low complexity profiles included in Korean broadcasting standard has a computation complexity of 2.8 times to 12.4 times that of the QMF synthesis operation in case of rendering as a channel signals, and it has a computation complexity of 4.1 times to 15.3 times of the QMF synthesis operation in case of rendering as a binaural signals.

• Journal of Radiation Protection and Research
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• v.37 no.1
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• pp.16-24
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• 2012

In the present study, a gamma-ray detector and associated signal processing circuit was developed for a side-absorber of a dual-mode Compton camera. The gamma-ray detector was made by optically coupling a CsI(Tl) scintillation crystal to a silicon photodiode. The developed signal processing circuit consists of two parts, i.e., the slow part for energy measurement and the fast part for timing measurement. In the fast part, there are three components: (1) fast shaper, (2) leading-edge discriminator, and (3) TTL-to-NIM logic converter. AC coupling configuration between the detector and front-end electronics (FEE) was used. Because the noise properties of FEE can significantly affect the overall performance of the detection system, some design criteria were presented. The performance of the developed system was evaluated in terms of energy and timing resolutions. The evaluated energy resolution was 12.0% and 15.6% FWHM for 662 and 511 keV peaks, respectively. The evaluated timing resolution was 59.0 ns. In the conclusion, the methods to improve the performance were discussed because the developed gamma-ray detection system showed the performance that could be applicable but not satisfactory in Compton camera application.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.129-138
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• 2014

This paper proposes a fast intra prediction method to reduce encoding time for the HEVC(high-efficiency video coding) encoder. The proposed fast Intra prediction method uses quadtree structure and SATD(Sum of Absolute Transformed Differences). In HEVC, a $8{\times}8$ SATD value using $8{\times}8$ hadamard transform is used to calculate a SATD value for $8{\times}8$ or larger blocks. The proposed method calculates the best SATD value by using each $8{\times}8$ SATD result in $16{\times}16$ or larger blocks. After that, the proposed method removes a candidate mode for RDO(Rate-Distortion Optimization) based on comparing SATD of the candidate mode and the best SATD. By removing candidate modes, the proposed method reduces the operation of RDO and reduces total encoding time. In $8{\times}8$ block, the proposed method uses additional $4{\times}4$ SATD to calculat the best SATD. The experimental results show that the proposed method achieved 5.08% reduction in encoding time compared to the HEVC test model 12.1 encoder with almost no loss in compression performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.31-37
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• 2001

Digital servo implementation in optical servo chip has been spotlighted since it is easy to integrate with other blocks and it has less sensitive characteristics change in terms of temperature variation and better flexibility to the system variation like pick-up. Therefore, Optical disc players adopted digital servo are increasing in market. However, one drawback of digital signal processor embedded digital servo is power consumption that is one of the most important factors of portable optical disc player system. For that reason, this paper introduces new architecture to reduce power consumption of digital servo by means of reducing DSP load but increasing minimum hardware size. The main idea of reducing power consumption of digital servo greatly is utilizing CDP characteristics as most operations are done and used up most operating steps of DSP at the initial time, but most power consumption is occurred in play mode. Therefore, if operating steps for digital filtering in play mode could be reduced greatly, power consumption of overall system can be reduced greatly. This paper shows an example that low power digital servo architecture whose current is reduced almost 83%, compare to that of digital servo which is not applied by the low power architecture introduced in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.103-110
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• 2010

In this paper, a new mode changeable asymmetric full bridge dc/dc converter is proposed to solve the freewheeling current problem of the conventional zero voltage switching(ZVS) phase shift full bridge(PSFB) dc/dc converter of low output voltage and high output current applications. The proposed converter is operated as an asymmetric full bridge converter when the duty cycle is less than 50% and active clamp full bridge converter when the duty cycle is greater than 50%. As a result, since its freewheeling current is eliminated, the conduction loss is lower than that of the conventional ZVS PSFB dc/dc converter. Moreover, ZVS of all power switches can be ensured along a wide load ranges and output current ripple is very small. Therefore, high efficiency of the proposed converter can be achieved. Especially since its operation mode is changed to the active clamp full bridge converter during hold up time and can be operated with 50~100% duty ratio, it can produce the stable output voltage along wide input voltage range. The operational principles, theoretical analysis and design considerations are presented. To confirm the operation, validity and features of the proposed converter, experimental results from a 1.2kW($400V_{dc}/12V_{dc}$) prototype are presented.

• Journal of Climate Change Research
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• v.2 no.3
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• pp.175-189
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• 2011

In this research, we describe the methodology and the quantification about GHG reduction effects, expected by optimization of operation mode according to establishing additional heat storage system of Bundang Combined Cycle Power Plant. As an intermediate form of General Combined Cycle Power Plant and Heat supply only district heating plant, Bundang Combined Cycle Power Plant(and Ilsan, Anyang, Bucheon) is possible to satisfy demand for the electrical load and thermal load capacity at the same time through changes to the operation mode itself. Therefore, through the operating transition of high-efficiency mode that the condenser cooling water is recovered and supplied to district heat and cooling, establishing additional heat storage system have flexible supply ability at the power and heat market. In this research, We calculated using the operating performance for the last three years(2008~2010) and efficiency of each mode-specific values. As a result, GHG reduction effects were calculated as $97.95kg_{-}CO_2/Gcal$ per heat energy 1 Gcal supplied at the heat storage system and we expected emmision reduction effect about $13,500Ton_{-}CO_2/yr$.