• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.587-597
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• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• Smart Media Journal
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• v.8 no.1
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• pp.19-26
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• 2019

At the opening ceremony of 2018 Winter Olympics in PyeongChang, an unknown cyber-attack occurred. The malicious code used in the attack is based on in-memory malware, which differs from other malicious code in its concealed location and is spreading rapidly to be found in more than 140 banks, telecommunications and government agencies. In-memory malware accounts for more than 15% of all malicious codes, and it does not store its own information in a non-volatile storage device such as a disk but resides in a RAM, a volatile storage device and penetrates into well-known processes (explorer.exe, iexplore.exe, javaw.exe). Such characteristics make it difficult to analyze it. The most recently released in-memory malicious code bypasses the endpoint protection and detection tools and hides from the user recognition. In this paper, we propose a method to efficiently extract the payload by unpacking injection through IDA Pro debugger for Dorkbot and Erger, which are in-memory malicious codes.

• Journal of the Korea Society of Computer and Information
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• v.25 no.10
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• pp.125-133
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• 2020

In this paper, we design 4-layer TCP/IP that utilizes minimal memory and processor resources in Internet of Things(IoT) systems. The TCP/IP designed in this paper has the following characteristics. First, memory resource is minimized by using minimal memory allocation. Second, processor resource is minimized by using minimal memory copy. Third, the execution time of the TCP/IP can be completed in a deterministic time. Fourth, there is no memory leak problem. The standard in minimal resources for memory and processor derived in this paper can be used to check whether the network subsystems of the already implemented IoT systems are efficiently implemented. As the result of measuring the amount of memory allocation and copy of the network subsystem of Zephyr, an open source IoT kernel recently released by the Linux Foundation, we found that it was bigger than the standard in minimal resources derived in this paper. The network subsystem of Zephyr was improved according to the design proposed in this paper, confirming that the amount of memory allocation and copy were decreased by about 39% and 67%, respectively, and the execution time was also reduced by about 28%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.65-71
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• 2007

Doherty amplifier has more efficiency and distortion than general amplifier. These distortion classified amplitude distortion and phase distortion, memory effect distortion. This paper reports on an attempt to investigate, model and quantity the contribution of the electrical nonlinearity effects and the thermal memory effects to a doherty amplifier's distortion generation and suggests thermal memory effect compensator for pre-distorter. Also this paper reports on the development of an accurate dynamic expression of the instantaneous junction temperature as a function of the instantaneous dissipated power. The parameters of suggested model suppress thermal memory effects doherty amplifier with pre-distorter. Pre-distorter with electrothermal memory effect compensator for doherty amplifier enhanced ACLR performance about 22 dB than general doherty amplifier. Experiment results were mesured by 50W LDMOS Doherty amplifier and pre-distorter with electrothermal memory effect compensator was simulated by ADS.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.61-68
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• 2011

Memory error debugging is one of the most critical processes in improving software quality. However, due to the extensive time consumed to debug, the enhancement often leads to a huge bottle neck in the development process of mobile devices. Most of the existing memory error detection tools are based on static error detection; however, the tools cannot be used in mobile devices due to their use of large working memory. Therefore, it is challenging for mobile device vendors to deliver high quality mobile devices to the market in time. In this paper, we introduce "PinMemcheck", a pin-based memory error detection tool, which detects all potential memory errors within $1.5{\times}$ execution time overhead compared with that of a baseline configuration by applying the Pin's binary instrumentation process and a simple data structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.5
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• pp.123-136
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• 2021

RPC (Remote Procedure Call)-based Graphics Processing Unit (GPU) virtualization technology is one of the technologies for sharing GPUs with multiple user virtual machines. However, in a cloud environment, unlike CPU or memory, general GPUs do not provide a resource isolation technology that can limit the resource usage of virtual machines. In particular, in an RPC-based virtualization environment, since GPU tasks executed in each virtual machine are performed in the form of multi-process, the lack of resource isolation technology causes performance degradation due to resource competition. In addition, the GPU memory competition accelerates the performance degradation as the resource demand of the virtual machines increases, and the fairness decreases because it cannot guarantee equal performance between virtual machines. This paper, in the RPC-based GPU virtualization environment, analyzes the performance degradation problem caused by resource contention when the GPU memory requirement of virtual machines exceeds the available GPU memory capacity and proposes a GPU memory management technique to solve this problem. Also, experiments show that the GPU memory management technique proposed in this paper can improve the performance of GPGPU tasks.

• The Journal of Korean Association of Computer Education
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• v.15 no.3
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• pp.37-47
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• 2012

One of the major goals in high school Informatics is for students to develop creative problem-solving abilities based on knowledge on computer science. Thus, the contents of the textbooks should be accurate and appropriate. However, we discovered that the current Informatics textbooks contain the untrue and/or inappropriate descriptions of main memory and virtual memory. The textbooks describe that main memory is composed of RAM and ROM. The virtual memory is described as a technique in which a part of the secondary storage is utilized as main memory to execute an application of which size is larger than that of main memory. In this study, we attempted to uncover the root causes of the fallacies, and suggest the accurate explanations by comparing with renowned books adopted in most schools worldwide including USA. Our study reveals that it is inappropriate to include ROM in main memory from the memory hierarchy perspective. Virtual memory is a technique that provides convenience to programmers, through which an operating system loads the necessary portion of a program from secondary storage to main memory. As for the advantages of virtual memory in the current computer systems, the focus should be on providing the effective multitasking capability, rather than on executing a larger program than the size of main memory. We suggest that it is appropriate to exclude virtual memory in textbooks considering its complexity.

• The Journal of the Korea Contents Association
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• v.15 no.4
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• pp.9-16
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• 2015

On modern operating systems such as Linux, virtual memory is a general way to provide a large address space to applications by using main memory and storage devices. Recently, storage devices have been improved in terms of latency and bandwidth, and it is expected that applications with large memory show high-performance if next-generation storage devices are considered. However, due to the overhead of virtual memory subsystem, the paging system can not exploit the performance of next-generation storage devices. In this study, we propose several optimization techniques to extend memory with next-generation storage devices. The techniques are to allocate block addresses of storage devices for write-back operations as well as to configure the system parameters, and we implement the techniques on Linux 3.14.3. Our evaluation through using multiple benchmarks shows that our system has 3 times (/24%) better performance on average than the baseline system in the micro(/macro)-benchmark.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.23-29
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• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.