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http://dx.doi.org/10.6109/jkiice.2021.25.12.1914

Optimization of FPGA-based DDR Memory Interface for better Compatibility and Speed  

Kim, Dae-Woon (Department of Electronics Engineering, Dong-A University)
Kang, Bong-Soon (Department of Electronics Engineering, Dong-A University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.25, no.12, 2021 , pp. 1914-1919 More about this Journal
Abstract
With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.
Keywords
Verilog HDL; FPGA verification; DDR memory; Double buffering; Finite state machine(FSM);
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