• Journal of KIISE
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• v.44 no.3
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• pp.223-231
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• 2017

In this paper, we study the performance of recently popular multi-core systems in mobiles. Previous research on the multi-core performance usually focused on the desktop PC. However, there is enough scope to further analyze heterogeneous multi-core systems. Therefore, by extending homogeneous multi-core systems, we analyze the heterogeneous multi-core systems using Size Interval Task Allocation (SITA) for job allocation, and Shortest Remaining Processing Time (SRPT) scheduling, for each individual core. We propose a new computational method regarding the cutoff point, which is crucial in analyzing SITA, by calculating the sojourn time. This facilitate easy and accurate calculation of the sojourn time. We further confirm our analysis through the ESESC simulator that provides actual measurements.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.13-21
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• 2013

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.325-326
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• 2013

전력 시스템과 관련된 연구에서 시뮬레이터는 과도 상태 해석을 위해 필수적이다. 보편적인 디지털 시뮬레이터는 오랜 수행 시간과 저장 메모리의 한계 때문에 대규모 시스템 해석에 부적합하다. 따라서 최근 출시되고 있는 고성능 멀티코어 DSP를 이용하여 실시간 디지털 시뮬레이터를 구현하였다. 구현된 시뮬레이터를 사용하여 선박 통합 전력 시스템을 모의하여 과도 및 정상 상태 해석을 수행하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1753-1756
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• 2010

최근 들어 가상화 기술은 서버의 통합에 뿐만 아니라, 임베디드 시스템에서도 널리 사용되고 있다. 하지만, 가상화 시스템에서는 물리 프로세서가 게스트 운영체제에게 직접 전달되지 않으며, 게스트 운영체제는 가상 프로세서를 통해서 실행할 수 밖에 없다. 따라서, 기존의 처리량 기준의 공평성 스케줄러가 가상머신 모니터에서 동작하는 경우, 실시간 스케줄링이 불가능하다. 본 연구에서는 멀티코어 기반의 가상화 시스템에서 실시간 태스크의 실행을 보장하는 기법을 소개한다. 특히, 본 논문에서는 계층형 스케줄링의 특성과 최대 병렬성 조건을 통하여 멀티코어 가상머신의 스케줄 가능성 분석 기법을 제시한다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.07a
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• pp.1-2
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• 2017

본 논문에서는 지휘무장통제체계(이하 CFCS) 소프트웨어의 성능 향상 기법으로 고성능 컴퓨팅(이하 HPC) 시스템 활용 기법을 제안한다. 이 기법으로 본 논문에서는 HPC 분야인 멀티코어 프로세서를 활용하는 방법을 제안한다. 복잡한 반복연산을 하는 작업이 많은 CFCS의 특정 SW모듈에 대해 멀티코어 프로세싱 아키텍처를 이용한 병렬처리를 적용하여 기존 순차처리 대비 작업실행시간을 단축함으로써 작업 응답시간을 상당히 줄일 수 있다. 본 논문에서는 CFCS 시험 환경의 일부 특정 SW모듈 상에서 기존의 순차처리 방식으로 수행한 연산 결과와 다중 처리 프로그래밍 API인 OpenMP를 적용하여 수행한 연산 결과를 비교하여 CFCS에서의 멀티코어 프로세싱이 체계 전반의 성능 향상 면에서 효율적으로 사용될 수 있음을 보인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.290-293
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• 2014

모바일 디바이스의 보급으로 사람들의 생활에 많은 변화를 가져왔으며, 이러한 변화에 따라 점차 수요에 따른 모바일 콘텐츠 시장 또한 확산 되었다. 사람들의 수요에 의해 모바일 애플리케이션은 문서작성, 게임, 사진, 은행 업무, 영화, 벨소리 뿐 아니라 HD 비디오 재생, 스트리밍 AV 서비스 등 하드웨어적 고성능을 요구하는 애플리케이션까지 등장하게 되었다. 이러한 추세에 더불어 모바일 디바이스는 멀티코어의 성능에 이르는 디바이스까지 출시 되었다. 하지만 멀티코어의 효율성은 스케쥴러가 코어에 작업을 할당하는 방법에 따라 달라진다. 이종 멀티 코어 플랫폼에서 애플리케이션의 실행 시간은 실행되는 코어에 의존한다. 본 논문에서는 프로파일에 의해 각 태스크의 실행 시간을 분석하여 태스크 스케쥴링 기법을 제안한다.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.11-19
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• 2012

In this paper, we propose a power-efficient scheduling scheme for lightly loaded multicore processors which contain more processing cores than running tasks. The proposed scheme activates a portion of available cores and inactivates the other unused cores in order to save power consumption. The tasks are assigned to the activated cores based on a heuristic mechanism for fast task assignment. Each activated core executes its assigned tasks with the optimal clock frequency which minimizes the power consumption of the tasks while meeting their deadlines. Evaluation shows that the proposed scheme saves up to 78% power consumption of the previous method which activates as many processing cores as possible for the execution of the given tasks.

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• Journal of KIISE
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• v.43 no.9
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• pp.1060-1065
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• 2016

Recently, there is an emerging need for parallel UHD video processing, and the usage of computing systems that have an asymmetric processor such as ARM big.LITTLE is actively increasing. Thus, a new parallel UHD video processing method that is optimized for the asymmetric multicore systems is needed. This paper proposes a novel HEVC tile partitioning method for parallel processing by analyzing the computational power of asymmetric multicores. The proposed method analyzes (1) the computing power of asymmetric multicores and (2) the regression model of computational complexity per video resolution. Finally, the model (3) determines the optimal HEVC tile resolution for each core and partitions/allocates the tiles to suitable cores. The proposed method minimizes the gap in the decoding time between the fastest CPU core and the slowest CPU core. Experimental results with the 4K UHD official test sequences show average 20% improvement in the decoding speedup on the ARM asymmetric multicore system.