• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.646-648
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• 1999

본 논문에서는 RSA 암호 알고리즘의 핵심 계산 과정인 모듈로 곱셈 연산의 효율적인 하드웨어 구현을 위해 새로운 알고리즘과 하드웨어 구조를 제시한다. 기존의 몽고메리 알고리즘이 LSB 우선 방법을 사용한 것과는 달리 여기서는 MSB 우선 방법을 사용하였으며, RSA 암호 시스템에서 키가 일정 기간 동안 변하지 않고 유지된다는 점에 착안해 계수(Modulus)에 대한 보수(Complements)를 미리 계산해 놓고 이를 이용하여 모듈로 감소 처리를 간단히 덧셈으로 치환하도록 하였다. 보수들을 저장할 몇 개의 레지스터와 그들 중 하나를 선택하기 위한 간단한 멀티플렉서(Multiplexer)만을 추가함으로써 몽고메리 알고리즘이 안고 있는 홀수 계수 조건과 사후 연산이라는 번거로움을 없앨 수 있다. 본 논문에서 제안하는 알고리즘은 하드웨어 복잡도가 몽고메리 알고리즘과 비슷하며 그 내부 계산 구조를 보여주는 DG(Dependence Graph)의 지역 연결성 (Local Connection), 모듈성(Modularity), 데이터의 규칙적 종속성 (Regular Data Dependency)등으로 인한 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.07a
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• pp.95-96
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• 2019

본 논문에서는 연결된 다양한 인터페이스를 갖는 비디오 카메라들 중에서 선택된 카메라의 영상을 통신망을 통해 다양한 다수의 외부 수신장치들에게 해당 영상을 전송하고 연결관리를 하는 영상송신시스템을 제안한다. 제안하는 송신시스템은 외부 비디오 카메라들의 연결을 위한 컴포지트 인터페이스와 범용 USB 카메라를 위한 USB 인터페이스, 유무선 송수신 및 ARM 계열의 CPU 모듈, 그 외에 개발을 위한 몇몇 장치들을 연결할 수 있도록 구성된다. 통신망릉 통해 제안한 송신시스템에 접속된 외부 수신장치들은 개별 채널을 할당 받아 특정 카메라 모듈을 선택하여 해당 영상을 수신할 수 있으며, 제안하는 송신시스템은 이를 위해 연결된 다수의 외부 수신장치들과의 연결관리 및 해당 카메라 모듈의 영상을 송신관리 등과 같은 기능으로 구성된다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.21-27
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• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.629-634
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• 2000

In this paper, we describe the structure of the DWMT (discrete wavelet multitone) transceiver for VDSL system. The DWMT transceiver consists of the transmultiplexer using cosine modulation filter bank (CMFB), time domain equalizer (TEQ) and frequency domain equalizer (FEQ) minimizing the effects of the transmission channel. For FEQ, we have expanded the conventional l-D linear transversal equalizer into 2-dimensions, i.e. time and subchannel axes and we have implemented it using the 2-dimensional LMS methods. In order to qualify the performance of FEQ, we have applied it to the DWMT based VDSL transceiver and the equalizer's performance is verified by simulation using the VDSL line test model specified by the ANSI T1E1.4 requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.7
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• pp.980-988
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• 1993

In this paper, performance of 8-ISDN traffic for the buffer size which is requested of important parameters in switch/multiplexer of B-ISDN with multimedia traffic is analyzed. Multimedia traffic is modeled as a traffic, which is composed of poisson distribution traffic and burst traffic with exponential/geometric ON time duration(Burst duration) Performance of traffic which is modeled as a multimedia traffic is analysed and buffer size, can provide the high quality service, is presented for the cell loss probability. It is simulated using event scheduling approach method which is provided by simulation package, PC SIMSCRIPT II.5. Simulation program is composed of PREAMBLE, MAIN, INITIAL, ARRIVAL, DEPARTURE and STOP·SIM modules. Specially, in case of mixed traffic simulation, ARRIVAL module is composed of ARRIVAL I and ARRIVAL II, and cells are generated independently by each module.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.145-151
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• 2003

This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.520-529
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• 2001

Carry-save-adder(CSA) is one of the most effective operation cells in implementing an arithmetic hardware with high performace and small circuit area. An fundamental drawback of the existing CAS applications is that the applications are limited to the local parts of arithmetic circuit that are directly converted to additions. To resolve the limitation, we propose a set of new CSA transformation techniques: optimizing arithmetics with multiplexors, optimizing arithmetics in multiple designs, and optimizing arithmetics with multiplications. We then design a new CSA transformation algorithm which integrates the proposed techniques, so that we are able to utilize CSAs more globally. An extensive experimentation for practical designs are provided to show the effectiveness of our proposed algorithm over the conventional CSA techniques.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.775-780
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• 2004

This paper describes the realization of the Ka-band group-delay equalized filter desisted with the help of a new hybrid method of Simulated Annealing(SA) and Conjugate Gradient(CG), to be employed by the multi-channel Input Multiplexer for a satellite use, each channel of which comprises a channel filter and a group-delay equalizer. The SA and CG find circuit parameters of an 8th order elliptic function filter and a 2-pole equalizer, respectively. Measurement results demonstrate that the performances of the designed component meet the specifications, and validate the design methods.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.599-605
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• 2003

A dual-mode asymmetric canonical filter is widely used in an input demultiplexer for satellite transponder. This paper deals with a simple synthesis method fur an asymmetric canonical filter. The coupling matrix of an asymmetric canonical filter is obtained by applying plane rotation technique to the coupling matrix of a symmetric canonical filter. This paper gives a list of pivots and rotation angles to obtain the coupling matrix of asymmetric canonical structure filters. The coupling matrix of 8th and 10th order asymmetric canonical filter is obtained by this proposed method. It is shown that the frequency response of asymmetric canonical filter is identical to that of symmetric canonical filter.