• Journal of Game and Entertainment
• /
• v.2 no.1
• /
• pp.8-16
• /
• 2006

The development of multicast communication services in the Internet is expected to lead a stable packet transfer even though On-Line Games generate heavy traffic. The Core Based Tree scheme among many multicast protocols is the most popular and suggested recently. However, CBT exhibits two major deficiencies traffic concentration or poor core placement problem. Thus, measuring the bottleneck link bandwidth along a path is important to understand the performance of multicast. We propose a method in which the core router's state is classified into SS(Steady State), NS(Normal State) and BS(Bottleneck State) according to the estimated link speed rate, and also the changeover of multicast routing scheme for traffic overload. In addition, we introduce Anycast routing tree, an efficient architecture for constructing shard multicast trees.

• Proceedings of the Korean Information Science Society Conference
• /
• 2007.06b
• /
• pp.412-417
• /
• 2007

멀티 포트 네트워크 인터페이스 카드는 지원 가능한 대역폭의 합이 포트의 수에 따라서 결정된다. 따라서 I/O 버스와의 대역폭 균형을 맞출 수 있는 장점이 있다. 또한 상대적으로 저렴한 스위치 가격으로 높은 대역폭을 지원해 줄 수 있다. 이러한 이유에서 최근 멀티 포트 네트워크 인터페이스 카드는 고 가용성 서버뿐만 아니라 고성능 서버에서도 사용되기 시작하고 있다. 본 논문에서는 이러한 멀티 포트 네트워크 인터페이스 카드가 지원할 수 있는 최대 대역폭을 분석한다. 특히 최근에 등장한 멀티 코어 프로세서 서버에서 TCP/IP 성능 측정을 수행하여 멀티 코어 자원을 최대한 활용하는지를 분석한다. 분석 결과 현재 리눅스가 제공하는 인터럽트 분산 정책 및 패킷 처리 기법으로는 멀티 포트 네트워크 인터페이스 카드의 높은 대역폭 특성을 최대한 활용하기에는 부족함을 밝힌다. 또한 각 포트 별로 들어오는 네트워크 흐름의 특성이 서로 다를 때에 시스템이 그에 신속히 적응하지 못함을 측정 결과를 통해서 보인다. 이러한 측정 및 분석 결과는 멀티 코어 시스템에서 멀티 포트 NIC을 최대한 활용하기 위한 리눅스의 향상 필요성을 시사하며 그를 위한 방안을 제시할 수 있다.

• Journal of the Korea Society of Computer and Information
• /
• v.19 no.4
• /
• pp.1-8
• /
• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Journal of Digital Contents Society
• /
• v.19 no.6
• /
• pp.1219-1224
• /
• 2018

Nowaday, smart mobile devices on Internet of Things are required to process and deliver greate amount of data in real-time. Therefore, heterogeneous mult-core architecture such the big.LITTLE core architecture, which shows high energy conservation while guaranteeing high performance, are widely employed on up to date smart mobile devices. The LITTLE cores should be highly utilized to gain higher energy conservation because LITTLE cores have much higher energy efficiency than big cores. In this paper, we propose a core selection algorithm, which tries to firstly assign a real-time task on a LITTLE core rather a big core while the task can be finished within its own deadline. We also perform simulation as performance evaluation to show that our proposed algorithm shows higher energy conservation while guaranteeing the required performance.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.10
• /
• pp.13-21
• /
• 2013

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.

• Journal of Platform Technology
• /
• v.10 no.2
• /
• pp.3-9
• /
• 2022

In this paper, to maximize the performance of the scatter communication in multi-core and many-core processors, a technique that considers the communication situation of the processing node is applied to a multi-core processor composed of 32 processing nodes. Since the existing scatter algorithm cannot recognize the communication conditions of the processing nodes, communication is generally performed according to an initially set transmission order. In this case, scatter communication starts only after the communication currently being performed by all processing nodes inside the processor is finished. The scatter communication performance was improved by this technique, and it was confirmed that there was a performance improvement of up to 78.93% compared to the existing algorithm through BFM simulation.

• Proceedings of the Korean Information Science Society Conference
• /
• 1998.10a
• /
• pp.205-207
• /
• 1998

본 논문은 유선망에서의 {{{{ {SM}^{ 2}A }}}} 무선 ATM 망으로 확장한 방안의 소개한다. {{{{ {SM}^{ 2}A }}}}는 기본적으로 양방향성 공유트리방식의 CBT(Core Baeed Tree)구조를 갖는다. 각 지역망(Regional Network))은 하나의 통신그룹단위를 형성하여 자체적인 코어스위치를 보유하고 이들 코어가 공붕망을 통해 연결되므로써 결과적으로 다중코어 구조를 갖는다. 한편, 무선 ATM 망에서 멀티캐스트 서비스를 제공은 유선망에서의 멀티캐스트 서비스제공방식과는 몇가지 점에서 차이를 가지며 보다 복잡하다. 즉, 동적 그룹관리, 멀티캐스트 채널의 재설정문제, 멀리캐스트 가입 호스트의 핸드오프(Handoff) 문제들이 해결되어야 하는데. {{{{ {SM}^{ 2}A }}}}에는 위의 다양한 문제들을 해결하였으며 더불어 인터넷 멀티캐스트 서비스를 무선망에서 수용하기 위한 안정적 데이터 전송 메커니즘도 제안한다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.14 no.8
• /
• pp.768-772
• /
• 2008

Today's microprocessor normally includes several processing cores to reduce the energy consumption without losing performance. In this paper, data transfer ordering mechanism can be efficiently used for cache coherence solution in unidirectional ring interconnect. RING-DATA ORDER combines the simplicity of GREEDY-ORDER and the performance of RING-ORDER. RING-DATA ORDER can be easily applicable to multicore processor with unidirectional ring interconnect.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.6
• /
• pp.259-265
• /
• 2014

When the trace-driven simulation is used for the performance analysis of widely used multicore processors in the initial design stage, much time and disk space is necessary. In this paper, statistical simulations are performed for a high performance multicore processor with various hardware configurations. For the experiment, SPEC2000 benchmarks programs are used for profiling and synthesizing new instruction traces. As a result, the performance obtained by our statistical simulation is comparable to that of the trace-driven simulation with the benefit of tremendous reduction in the simulation time.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.2
• /
• pp.157-163
• /
• 2016

If trace-driven or execution-driven simulation is used for the performance analysis of asymmetric multi-core processors, excessive time and much disk space are necessary. In this paper, statistical simulations are performed for asymmetric multi-core processors with various hardware configurations. For the experiment, SPEC 2000 benchmark programs are used for profiling and synthesis, which is supplied as input for the simulation of asymmetric multi-core processors. As a result, the performance of asymmetric multi-core processor obtained by statistical simulation is comparable to that of the trace-driven simulation with a tremendous reduction in the simulation time.