• Journal of Korea Technology Innovation Society
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• v.9 no.1
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• pp.131-148
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• 2006

With the rapid penetration of digital technology In recent years, there are growing expectations that many new services will soon become available. One of the new services is 3Dimension(3D) services, because our concern is concentrated on the quality of information that exceeds the digitalization of information. A stereoscopic technique for generating 3D images is contributed to raise the quality of Information and Communication Technology(ICT) service and is extensively applied to various fields. So 3D services, based on that technique, are expected to create a new market for ICT industry and provide significant benefits to consumers. The purpose of this paper is to analyze the consumer preference and evaluate the economic value of the 3D broadcasting service, so it provides propriety of the 3D technology development for market planners and product developers who need to assess the market potential of a product that is not yet available for actual test marketing. And it is useful for decision-makers in considering the provision of 3D services. In this paper, the gang survey was conducted to understand consumer preference of 3D services. And it attempts to apply the contingent valuation method(CVM) to measuring the willingness to Pay(WTP) for the 3D broadcasting service and analyzing the determinants of the WTP.

• Journal of Convergence Society for SMB
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• v.2 no.1
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• pp.51-58
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• 2012

Android platform is a powerful operating system developed on Linux 2.6 Kernel, and provides many features such as comprehensive libraries, a multimedia environment, and powerful interface for phone applications. Since Android is an open operating system, which can be installed in any vendors's equipments. Current smartphones as well as netbooks, navigations, car PCs, tablet PCs, Industrial PCs are used in various fields. It is difficult a lot that to mount to other devices on the Android platform or new devices. In this Paper, The process that data that occurred from a hardware was passed to the highest application and Android platform system for managing hardware devices were analyzed. Building Android & driver compilation environment, How to support the protocol for the use of WiFi in the kernel, How to Mount a WiFi device in the kernel, Device driver registration for the Android platform, WiFi Management Service Daemon (wpa_supplicant) and IP allocation services daemon (dhcpcd) registration, How to create a socket for communication between the daemon (wpa_supplicant) and HAL have been presented. In the experiment using the proposed method, WiFi devices were mounted on the Android platform in the X-86 & ARM family. Understanding the whole process of control flow in Android hierarchy is very important to porting a new device on it. The process included in this paper can help technicians who might encounter the obstacles in their porting works.

• Korean Business Review
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• v.18 no.2
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• pp.133-149
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• 2005

DAB is meeting with mixed success. Denmark is performing similarly to the UK thanks to the innovation of the public broadcaster but where DAB is not so strong, the problem can usually be pointed at the lack of enabling regulation. The UK's example, whilst not appropriate everywhere, has valuable lessons including licensing incentives for existing analogue commercial broadcasters and a market-building obligation on the national multiplex licensee. Despite the obvious success of DAB, it would be an omission to leave some of the continued criticisms unanswered, whether of its slow start or the underlying technology. True, there was much over-optimism in the mid-1990s, coupled with unrealistic promises and expectations of receiver pricing and consumer take-up. Governments across Europe have legislated for DAB digital radio in a variety of ways but few as successfully as the UK. It is essential that both public and private broadcasters are encouraged equally to participate in digital radio. The UK is fortunate because, for the last 10 years, there has been a progressive government policy towards digital broadcasting. The 1996 Broadcasting Act set out a full licensing regime for both digital television and digital radio. The 1996 UK legislation contained a number of key elements which have been cornerstones of its success. DAB digital radio began test broadcasting around ten years ago but it has not been a universal consumer success across Europe. In the UK, however, digital radio receivers are one of the fastest-selling consumer electronics products and sales have overtaken those of analogue radios. Why has the UK succeeded with DAB digital radio when other European countries have yet to see their markets take off? This article explains what steps the UK took to make DAB digital radio a success.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.722-737
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• 2002

As the number of multimedia applications increases, various protocols and architectures have been proposed to provide QoS(Quality of Service) guarantees in the Internet. Most of these techniques, though, bear inherent contradiction between the scalability and the capability of providing QoS guarantees. In this paper, we propose a protocol, named DQSP(Dynamic QoS Support Protocol), which provides the dynamic resource allocation and admission control for QoS guarantees in a scalable way. In DQSP, the core routers only maintain the per source-edge router resource allocation state information. Each of the source-edge routers maintains the usage information for the resources allocated to itself on each of the network links. Based on this information, the source edge routers perform admission control for the incoming flows. For the resource reservation and admission control, DQSP does not incur per flow signaling at the core network, and the amount of state information at the core routers depends on the scale of the topology instead of the number of user flows. Simulation results show that DQSP achieves efficient resource utilization without incurring the number of user flow related scalability problems as with IntServ, which is one of the representative architectures providing end-to-end QoS guarantees.

• Journal of KIISE:Software and Applications
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• v.30 no.1_2
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• pp.19-30
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• 2003

Based upon XML, a standard document format on the web, there have been many active studies on e-Commerce, wireless communication, multimedia technology and so forth. JML is an XML application suitable for understanding and reusing the source code written using JAVA for various purposes. And it is a DTD which can effectively express various information related to hierarchical class structures, class/method relationships and so on. This paper describes a tool which generates JML document by extracting a comment information from Java source code and information helpful for reusing and understanding by JML in terms of the reverse engineering and a tool which generates a skeleton code of Java application program from the document information included in the automatically or manually generated JML document in terms of the forward engineering. By using the result of this study, the information useful and necessary for understanding, analyzing or maintaining the source code can be easily acquired and the document of XML format makes it easy for developers and team members to share and to modify the information among them. And also, the Java skeleton coed generated form JML documents is a reliable robust code, which helps for developing a complete source code and reduces the cost and time of a project.

• The Journal of Society for e-Business Studies
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• v.16 no.4
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• pp.197-220
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• 2011

The smartphone is simply beyond the means of communication equipment, to line up the turning point of mobile convergence, is recognized as a service tool of new concept the camera, game, multimedia function, digital multimedia broadcasting, mobile internet etc, that use of smartphone is working toward developed a variety and new business models. The study is empirically studied casualties that self-determination influences flow and satisfaction which is intrinsic motivation of smartphone. There are many studies on flow, is intrinsic motivation, influencing satisfaction and Loyalty, but there are little studies which variables influences flow. this study is explore causality of autonomy, competence, relatedness which are major variables of self-determination theory that studied factors effecting intrinsic motivation influencing flow and satisfaction. This study developed a research model to explain the use of smartphone, and collected 670 survey responses from the office workers of seoul S company who had experiences with such smartphone. To prove the validity of the proposed research model, SEM analysis is applied with valid 670 questionnaires. The results, firstly, autonomy positively influences flow. secondly, competence significantly influences flow. thirdly, relatedness significantly influenced flow. also, upper above results shows that flow influences satisfaction.