• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1157-1164
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• 2006

In this paper, we proposed a method for measuring accurate positions and sizes of package and balls in a micro BGA. To find defects of BGA accurately, we focused on finding positions of package and balls. After labeling, we detected connected components of package and balls using feature parameters. After the detection of package component, we measured position and size of package by employing rectangular model which was constructed by the package information. After the detection of the ball components, we measured positions and diameters of balls by employing circular models which were constructed by the ball informations. We did calibration based on landmarks to measure real length, and we compared the measured results with the SEM data. Finally, we found that the accuracy of the proposed method is 94% in terms of ball's radius.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.145-164
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• 2004

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.05a
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• pp.54-69
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• 1999

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.87-126
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• 1999

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.117-120
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• 2002

In this paper, several methods to predict the solder joint shape are studied. Although there are various methods to predict the solder joint shape, such as truncated sphere method, force-bal tranced analytical solution, and energy-based methods like surface evolver developed by Ken Brakke, we calculate solder joint shape of $\mu$BGA by two solder joint shape prediction methods(truncated sphere method and surface evolver) and then compare results of each method. The results in dicate that two methods can accurately predict the solder joint shape in an accurate range. After that, we calculate reliability solder joint shape under thermal cycle test by FEA program ANSYS. As a result, it could be found that optimal solder joint shape calculated by solder joint prediction method has best reliability in thermal cycle test.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.27-32
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• 2002

In this paper, global full 3D finite element analysis fatigue models are constructed for flip-chip BGA on board to predict the creep fatigue life of solder joints during the thermal cycling test. The fatigue model applied is based on Darveaux's empirical equation approach with non-linear viscoplastic analysis of solder joints. It was estimated by the creep life as the variations of the four kinds of thermal cycling test conditions, pad structure, composition and size of solder ball. The shortest fatigue life of results was obtained at the thermal cycling testing condition of -65℃ ∼ 150℃. It was increased about 3.5 times in comparison with that of 0℃ ∼ 100℃. As the change of pad structure at the same other conditions, the fatigue life of SMD structure increased about 5.7% as compared with NSMD structure. Consequently, it was confirmed that the fatigue life became short as the creep strain energy density increased in solder joint.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.