• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.121-127
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• 2022

Micro-LED is a light-emitting diode smaller than 100 ㎛ in size. It attracts much attention due to its superior performance, such as resolution, brightness, etc., and is considered for various applications like flexible display and VR/AR. Micro-LED display requires a mass transfer process to move micro-LED chips from a LED wafer to a target substrate. In this study, we proposed a vacuum chuck method as a mass transfer technique. The vacuum chuck was fabricated with MEMS technology and PDMS micro-mold process. The spin-coating approach using a dam structure successfully controlled the PDMS mold's thickness. The vacuum test using solder balls instead of micro-LED confirmed the vacuum chuck method as a mass transfer technique.

• Clean Technology
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• v.18 no.3
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• pp.295-300
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• 2012

Synthesis of well-defined particle with tunable size, shape, and functionalities is strongly emphasized for various applications such as chemistry, biology, material science, chemical engineering, medicine, and biotechnology. This study presents micromolding method for the fabrication of anisotropic particles with elegant control of curvature of covex roof. For the demostration of rapid fabrication of the particles, we have applied polydimethylsiloxane (PDMS) micromold as structure guiding template and wetting fluid to control curvature of roof of the particles. Based on this approach, we can control the radius of curvature from $20{\mu}m$ to $70{\mu}m$ with different aspect ratio of mold. In addition, wetting fluids with different wetting properties can also modulate the height and radius of curvature of the particles. We envision that this methodology is promising tool for precise control of particle shape in 3-dimensional space and new synthetic route for anisotropic particles with cost effective, simple, easy, and fast procedure.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.5
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• pp.32-37
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• 2004

Polishing processes are widely used in the glass, optical, die and semiconductor industries. Chemical Mechanical Polishing (CMP) especially is becoming one of the most important ULSI processes for the 0.25m generation and beyond. CMP is conventionally carried out using abrasive slurry and a polishing pad. But the surface of the pad has irregular pores, so there is non-uniformity of slurry flow and of contact area between wafer and the pad, and glazing occurs on the surface of the pad. This paper introduces the basic concept and fabrication technique of the next generation CMP pad using micro-molding method to obtain uniform protrusions and pores on the pad surface.

• Korean Chemical Engineering Research
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• v.46 no.6
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• pp.1100-1106
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• 2008

In this study, we presented rapid and simple fabrication method of functionalized surface on various substrates as a universal platform for the selective immobilization of cells. The functionalized surface was achieved by using deposition of polyelectrolyte such as poly(allyamine hydrochloride) (PAH), poly(diallyldimethyl ammonium chloride) (PDAC), poly(4-ammonium styrene sulfonic acid) (PSS), poly(acrylic acid) (PAA) and fabrication of poly(ethylene glycol) (PEG) microstructure through micro-molding in capillaries (MIMIC) technique on each glass, poly(methyl methacrylate) (PMMA), polystyrene (PS) and poly(dimethyl siloxane) (PDMS) substrate. The polyelectrolyte multilayer provides adhesion force via strong electrostatic attraction between cell and surface. On the other hand, PEG microstructures also lead to prevent non-specific binding of cells because of physical and biological barrier. The characteristic of each modified surface was examined by using static contact angle measurement. The modified surface onto several substrates provides appropriate environment for cellular adhesion, which is essential technology for cell patterning with high yield and viability in the micropatterning technology. The proposed method is reproducible, convenient and rapid. In addition, the fabrication process is environmentally friendly process due to the no use of harsh solvent. It can be applied to the fabrication of biological sensor, biomolecules patterning, microelectronics devices, screening system, and study of cell-surface interaction.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2002.02a
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• pp.253-259
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• 2002

Micro cell structures with high aspect ratio were fabricated by injection molding method. The mold inserts had dimension $1.9cm\times8.3cm$ composed of a lot of micro posts and were fabricated by LIGA process. The size of the micro posts was $157{\mu}m\times157{\mu}m\times500{\mu}m$ and the gaps between two adjacent posts were $50{\mu}m$. Using Polymethylmethacrylate (PMMA) injection molding was performed. The key experimental variables were temperature, pressure, and time. By controlling these, good shaped mim cell structures with $50{\mu}m$ in wall thickness and $500{\mu}m$ in depth were obtained. In order to understand micro molding mechanism, shape changes of molded PMMA were studied with experimental variables. And the durability of mold insert was investigated, too. The results show that the most important factor in molding processes was the mold temperature that is closely related to the filling of the melt into the micro cavity. And the holding time before cooling showed a great effect on the quality of molded PMMA.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.351-354
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• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.

• Korean Chemical Engineering Research
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• v.58 no.1
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• pp.122-126
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• 2020

In this study, we produced the micropatterned channel system using polydimethylsiloxane (PDMS) and micromolding in capillaries (MIMIC) technology and evaluated cellular polarity signals through high-resolved imaging at the single-cell level. In cells treated with platelet-derived growth factor (PDGF), three types of key signals in cell migration; phosphoinositide 3-kinase (PI3 K), Rac, and Actin, were strongly activated in the front area compared to the rear region, whereas myosin light chain (MLC) showed no notable activity in the front and rear areas. Our results will, therefore, provide important information and methodology for studying the correlation between cell polarity signals and cell migration under the newly defined microenvironment.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.41-45
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• 2018

We have simulated the process induced warpage for panel level package using finite element method. Silicon chips of $5{\times}5mm^2$ were redistributed on $122.4{\times}93.6mm^2$ size panel and the total number of redistributed chips was 221. The warpage at each process step, for example, (1) EMC molding, (2) attachment of detach core, (3) heating, (4) removal of a carrier, and (5) cooling was simulated using ANSYS and the effects of detach core and carrier materials on the warpage were investigated. The warpage behaved complexly depending on the materials for the detach core and carrier. However, glass carrier showed the lower warpage than FR4 carrier regardless of detach core material, and the minimum warpage was observed when the glass was used for the detach core and carrier at the same time.