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http://dx.doi.org/10.6117/kmeps.2018.25.4.041

Process Induced Warpage Simulation for Panel Level Package  

Moon, Ayoung (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Kim, Sungdong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Publication Information
Journal of the Microelectronics and Packaging Society / v.25, no.4, 2018 , pp. 41-45 More about this Journal
Abstract
We have simulated the process induced warpage for panel level package using finite element method. Silicon chips of $5{\times}5mm^2$ were redistributed on $122.4{\times}93.6mm^2$ size panel and the total number of redistributed chips was 221. The warpage at each process step, for example, (1) EMC molding, (2) attachment of detach core, (3) heating, (4) removal of a carrier, and (5) cooling was simulated using ANSYS and the effects of detach core and carrier materials on the warpage were investigated. The warpage behaved complexly depending on the materials for the detach core and carrier. However, glass carrier showed the lower warpage than FR4 carrier regardless of detach core material, and the minimum warpage was observed when the glass was used for the detach core and carrier at the same time.
Keywords
warpage; FEM; PLP; carrier; detach core;
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Times Cited By KSCI : 1  (Citation Analysis)
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