• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.15-24
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• 2000

This paper presents an output feedback robust H$\infty$ control problem for a class of uncertain nonlinear systems, which can be represented by an fuzzy dynamic model. The nonlinear system is represented by Takagi-Sugeno fuzzy model, and the control design is carried out on the basis of the fuzzy model. Using a single quadratic Lyapunov function, the globally exponential stability and disturance attenuation of the closed-loop fuzzy control system are discussed. Sufficient conditions for the existence of robust H$\infty$ controllers are given in terms of linear matrix inequalities(LMIs). Constructive algorithm for design of robust H$\infty$ controller is also developed. The resulting controller is nonlinear and automatically tuned based on fuzzy operation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.127-133
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• 2004

A feedforward amplifier, which is composed of several components, is an open loop system. Therefore, feedforward amplifiers are apt to deteriorate its performance according to the environmental changes even though the cancellation performance and the linearization bandwidth of feedforward systems are superior to other linearization methods. A control method is needed for maintaining the original performance of feedforward amplifiers or to keep the desired performance within a little error bounds. In this paper, an adaptive control method using the steepest descent algorithm, which has a good convergence characteristic and is easy to implement, is suggested. The characteristics of the suggested control method compare with the characteristics of other control methods and the simulation results are presented.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.72-78
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• 2005

This paper describes the design of a robust output-feedback controller for a single-input single-output nonlinear dynamical system with a full relative degree. While all the previous research works on the output-feedback control are based on dynamic observers, a new state estimator which uses the past values of the measurable system output is proposed. We name it backward-difference state estimator since the derivatives of the output are estimated simply by backward difference of the present and past values of the output. The disturbance generated due to the error between the estimated and real state variables is compensated using an additional robustifying control law whose gain is tuned adaptively. Overall control system guarantees that the tracking error is asymptotically convergent and that all signals involved are uniformly bounded. Theoretical results are illustrated through a simulation example of inverted pendulum.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.671-680
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• 2005

The CFL linearisation chip which is one of key devices in ultra-narrowband mobile radio transmitter using CQPSK digital modulation method is designed and implemented with $0.35{\mu}m$ CMOS technology. The reduced size and low cost of transmitter are available by the use of direct-conversion and CFL ASIC chip, which improve the power effi챠ency and linearity of transmitting path. In addition, low power operation is possible through CMOS technology The performance test results of transmitter show -25 dBc improvement of IMD level at the 3 kHz frequency offset and then satisfy FCC 47 CFR 90.210 E emission mask in the operation of CFL ASIC chip. At that time, the transmitting power is about PEP(Peak-to-Envelope Power) 5 W. The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.