• Korean Journal of Optics and Photonics
• /
• v.13 no.2
• /
• pp.113-116
• /
• 2002

We demonstrate 16 ch.$\times$2.5 Gb/s WDM transmission over 10,880 km using a re-circulating loop and forward error correction (FEC) code. The performances of all 16 channels were measured to be lower than 10$^{-10}$ .

• Proceedings of the Korea Information Processing Society Conference
• /
• 2001.04a
• /
• pp.231-234
• /
• 2001

본 논문은 다단계 상호연결망에서 높은 처리율과 결함 허용을 위해 중복 경로를 제공하는 E-Cube-network 구조를 제안한다. Cube network의 확장된 형태인 E(Extended)-Cube network 구조를 통해 패킷 전송중 충돌이 발생한 경우 스위치 자신을 순환하고, 재차 충돌이 발생하면 멀티플렉서를 통해 또 다른 새로운 경로로 패킷을 전송하는 새로운 알고리즘을 제시한다. 그리고 모의실험을 통해 기존의 Cube network 구조보다 높은 종단간 처리율을 보인다.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2000.12a
• /
• pp.165-168
• /
• 2000

In this paper, we propose a method, an optimized architecture of a device with an image signal process of a field unit to minimize the flick phenomenon that happens in direction of a color temperature at a color tone change. The proposed IIR loop filter has an optimized architecture and reduced hardware compared with previous filters. In order to achieve the optimization for the hardware complexity. It is designed by time-multiplexing architecture. The proposed IIR loop filter is synthesized by using the STD90 0.35um cell library.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.69-76
• /
• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.4
• /
• pp.285-292
• /
• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Journal of KIISE:Software and Applications
• /
• v.34 no.5
• /
• pp.487-501
• /
• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.24 no.8
• /
• pp.70-77
• /
• 2010

This paper presents the current and speed controller design procedure and their performance for the IPMSM based next generation high speed railway traction system. The next generation high speed railway system is a power distributed type and uses vector control method for a motor speed control. Since the speed and current controller gains of the vector control system directly affects to the transient characteristics and speed control capability, the systematic design of the controllers are required. In this paper the controllers are designed using the IPMSM based next generation high speed railway system parameters. Simulation programs based on Matlab/Simulink is developed. Finally the controller characteristics are analyzed by the simulation results.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.35 no.5
• /
• pp.525-531
• /
• 2011

Exhaust gas recirculation (EGR) is more effective than selective catalytic reduction (SCR) or lean $NO_x$ trap (LNT) for the reduction of $NO_x$ emissions in diesel engines. A large amount of EGR gas is necessary to satisfy the stringent regulations on $NO_x$ emissions. Low pressure loop (LPL) EGR is almost independent of the variable geometry turbocharger (VGT) at a specific boost pressure, so LPL EGR is better than conventional high pressure loop (HPL) EGR in terms of EGR supply. We compare the influence of HPL EGR and LPL EGR on the combustion characteristics at a constant boost pressure in a diesel engine. The dilution ratio was employed as an independent parameter to analyze the effect of the dilution of the intake charge for each EGR loop. At the same level of $NO_x$ emissions, the fuel consumption and smoke opacity were slightly lower for LPL EGR than for HPL EGR.

• Korean Chemical Engineering Research
• /
• v.56 no.2
• /
• pp.169-175
• /
• 2018

This study deals with a process for the recovery of hydrogen isotopes from methane ($CQ_4$) and water ($Q_2O$) containing tritium in the nuclear fusion exhaust gas (Q is Hydrogen, Deuterium, Tritium). Steam Methane Reforming and Water Gas Shift reactions are used to convert $CQ_4$ and $Q_2O$ to $Q_2$ and the produced $Q_2$ is recovered by the subsequent Pd membrane. In this study, one circulation loop consisting of catalytic reactor, Pd membrane, and circulation pump was applied to recover H components from $CH_4$ and $H_2O$, one of $CQ_4$ and $Q_2O$. The conversion of $CH_4$ and $H_2O$ was measured by varying the catalytic reaction temperature and the circulating flow rate. $CH_4$ conversion was 99% or more at the catalytic reaction temperature of $650^{\circ}C$ and the circulating flow rate of 2.0 L/min. $H_2O$ conversion was 96% or more at the catalytic reaction temperature of $375^{\circ}C$ and the circulating flow rate of 1.8 L/min. In addition, the amount of $CQ_4$ generated by Korean Demonstration Fusion Power Plant (K-DEMO) in the future was predicted. Then, the treatment process for the $CQ_4$ was proposed and HAZOP (hazard and operability) analysis was conducted to identify the risk factors and operation problems of the process.

• Korean Journal of Construction Engineering and Management
• /
• v.6 no.3 s.25
• /
• pp.144-155
• /
• 2005

Since 1950s, the Korean housing market has continually experienced the chronicle lack of housing stock because of lower housing investment in comparison with a population explosion, prompt urbanization and rapid restructuring of family. The Korean housing market have thus been driven not by the pricing model by housing demand-supply chain but by the Korean housing policies focusing on the increase of housing supply and the living stability of the middle or low-income bracket. After all, repetitive economic vicious circle of housing price and the increase of unsold apartments aggravated the malfunction of the Korean housing market. Meanwhile, the Korean construction firms have exacerbated their profitability. Such terrible situations are mainly triggered by the Korean construction firms that weighed on the short-term profits and quick response of the government policy alterations rather than the prospect of housing market Therefore, this research focusing on the dynamics of housing market identified and classified the demand and supply elements that consist not only of housing system structures but also of the environmental elements that affect the structures. Based on the system thinking and traditional theory of consumer's choice, the interactions of these elements were constructed as a causal loop diagram that explains the mutual influences among housing subsystems with feedback loops. This paper describes and discusses about the causes of the dynamic changes in the Korean housing market. This study would help housing suppliers, including housing developers, construction firms, etc., to form a more comprehensive understanding on the fundamental issues that constitute the Korean housing market and thereby increasing their long term as well as minimizing the risk involved in the housing supply businesses.