• The Magazine of the IEIE
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• v.11 no.2
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• pp.1-11
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• 1984

본 지 2월호에서 구술한 선형부호에 이어 이번호에서는 순회부호에 대해 기술하고자 한다. 선형블럭부호중 중요한 부류에 속하는 순회부호(cyclic code)는 그 내용이 대수적 구조를 갖고 있어 부호화 회로는 물론 부호에 필요한 오증(syndrome)계산회로 등 귀환연결이 있는 치환레지스터(shift register)를 사용한 장치화(implementation)가 매우 용이하다는 이점이 있다. 이런 순회부호는 산발오진(random error)뿐 아니라 연집오진(burst error)도 정정할 수 있는 매우 효과적인 부호로서 다중오진정정능력(multiple error correcting capability)을 갖는 BCH부호도 순회부호의 일종이다.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.649-651
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• 1999

본 논문에서는 각종 암호계에 중요하게 이용되는 난수를 클라이언트-서버 환경에서 생성하는 방법에 대해 연구하였다. 완벽하게 랜덤으로 생성되는 난수를 만든다는 것은 불가능하므로, 난수를 발생시키는 알고리즘의 목표는, 입수할 수 있는 정보만으로는 예측 불가능한 랜덤성을 가지는 것이다. 여기서는 클라이언트-서버 환경의 특징을 이용해 돌연변이를 만들어 좀 더 강한 랜덤성을 지니는 난수의 생성을 조합 시프트 레지스터를 이용해 연구하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.950-953
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• 2015

본 논문에서는 HEVC 디코더에서 화면간 예측의 보간 필터에 대한 하드웨어 구조를 제시하고, 설계 및 분석결과를 통해 연구 결론을 도출하는 것이 목적이다. 제안하는 하드웨어 구조는 보간 필터의 각 필터 간의 유사성을 확인하고 빠르게 데이터를 처리하기 위한 병렬처리 방법을 제시한다. 또한 레지스터를 통한 데이터를 재사용하는 방식을 이용하여 외부 메모리와의 불필요한 연결을 줄여 성능을 향상시켰다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.734-737
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• 2008

This paper presents a new automatic TFT-LCD image quality optimization system. We also have developed new algorithms using 6-point programmable matching technique with reference gamma curve, and automatic power setting sequence. It optimizes automatically gamma adjustment and power setting registers in mobile TFT-LCD driver IC to reduce gamma correction error, adjusting time, and flicker. Developed algorithms and programs are generally applicable for most of the TFT-LCD modules. The proposed optimization system contains module-under-test (MUT, TFT-LCD module), control program, multimedia display tester for measuring luminance and flicker, and control board for interface between PC and TFT-LCD module. The control board is designed with DSP, and it supports various interfaces such as RGB and CPU. Developed automatic image quality optimization system showed significantly reduced gamma adjusting time, reduced flicker, and much less average gamma error than competing system. We believe that the proposed system is very useful to provide high image quality TFT-LCD and to reduce developing process time using optimized gamma-curve setting and automatic power setting.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.51-58
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• 2014

A LFSR is commonly used for various stream cryptography applications to generate random numbers. A Leap-ahead LFSR was presented to generate a multi-bits random number per cycle. It only requires a single LFSR and it has an advantages in hardware complexity. However, it suffers from the significant reduction of maximum period of the generated random numbers. This paper presents the new segmented Leap-ahead LFSR to solve this problem. It consists of two segmented LFSRs. We prove the efficiency of the proposed segmented architecture using the precise mathematical analysis. We also demonstrate the proposed comparison results with other counterparts using Xinilx Vertex5 FPGA. The proposed architecture can increase 2.5 times of the maximum period of generated random numbers compared to the typical Leap-ahead architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.245-251
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• 2015

In this paper, we present a design of PWM-controlled driving device for backlights in LED systems. The system can control either the brightness of the entire screen of backlights of LCD driven by LED or illumination or contrast of each partial segment of the entire screen. The PWM-controlled driving device includes the shift register that shifts the series data according to the clock signal prior to the generation of parallel data. It is also is comprised of a number of registers, a number of counters, a number of comparators, and a number of synchronizing gates (producing the PWM-controlled signals). The proposed device for backlights in LED systems can generate the PWM-controlled signal with a high degree of resolution without the increase of clock frequency. It also contains the PWM-controlled circuit that disperses and restrains the quantized noise.

• Korean Journal of Materials Research
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• v.7 no.10
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• pp.877-883
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• 1997

Ar 및 Ar과 $N_{2}$ 분위기하에서 rf 마그네트론 스퍼터링방법으로 Ta-AI과 Ta-AI-N합금막을 제조하였다. Ta-7.9at.% AI계열, Ta-26.7 at% AI게열과 Ta-45.4at.%AI계열에 Ar에 대한 질서유량비로 26%까지 질소를 첨가하여 Ta-AI-N박막을 증착한후, 300-$600^{\circ}C$온도 구산에서 열처리 전후의 구조 및 전기적 특성과 열적안정성을 통하여 레지스터의 적용가능성을 조사하였다. 구조 및 조성 분석은 X-선 회절과 Rutherford Backscattering Spectrometry(RBS)로 관찰하였고 열적안정성은 4단자법(four point probe method)을 이용한 저항변화를 통하여 측정하였다. 순수 Ta에 AI을 첨가하면 확장된 $\beta$($\beta$-Ta)N 합금박막에서 가장 열적안정성이 우수하게 나타났던 질소첨가 범위는 Ta $N_{hcp}$또는 TaN/ sub fcc/또는 Ta $N_{fcc}$와 비정질과의 혼합상순으로 상천이를 나타내었다. Ta-AI-N 합금박막에서 가장 열적안정성이 우수하게 나타났던 질서첨가 범위는 Ta-26.7at. % AI계열의 경우 19-36at.% $N_{2}$구간이었고, Ta-45.5at.% AI계열의 경우는 30-45at.%구간이었다. Ta-AI합금박막은 질소가 첨가되지 않아도 열처리 온도 및 시간에 따라 약 10% 이내의 비교적 작은 저항변화를 보여 열적안정성이 우수하지만 질소를 첨가하여 Ta-AI-N합금박막을 형성시킬경우, 증착된 상태에서 이미 큰 비저항을 나타내었고 열처리 동안 3%이내의 매우 작은 저항변화를 나타내었기 때문에 레지스터용 재료로써 열적안정성에 대한 잠재력이 크다.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.498-503
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• 2017

SIMD (Single Instruction Multiple Data) is a representative parallelization architecture that processes multiple data loaded in a SIMD register with a single instruction. Quicksort is a sorting algorithm that picks an element as a pivot from the array and reorders the array such that all elements having the values less than the pivot value are located in the left side on the pivot as well as all elements having the value greater than the pivot value are located in the right side on the pivot and then the algorithm performs the same task on both sublist recursively. In this paper, we propose an efficient Quicksort algorithm applying the SIMD instructions which minimally invokes conditional branches to avoid the performance degradation incurred by branch misprediction in a pipeline architecture. In addition, we improve the performance of the Quicksort algorithm by fetching data into a SIMD register as a byte unit to apply VBP (Vertical Bit Parallel) and the early pruning technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.