• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.399-400
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• 2008

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.51-54
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• 2000

In this paper, an compiler system is ported and modified for register allocation experiments. This compiler system will enable various global register allocation. Lcc is introduced and Chaitin's graph coloring algorithm is executed with cmcc on DEC ALPHA 255/300. Several functions of SPEC921NT is used as inputs of the compiler system.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.413-415
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• 1998

스택 머신 코드(stack-machine code)를 레지스터 기반 언어로 변환하는데 있어 스택의 타입 정보가 있으면 보다 효율적인 코드를 생성할 수 있음을 알아내었다. 본 논문에서는 스택 머신 코드의 타입을 분석해야 할 이유를 제기하고, 요약해석 방법론에 따라 분석 방법을 제시하고, 제시된 분석 방법의 안전성을 짚어 본다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.655-656
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• 2007

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.251-252
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• 2010

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.3
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• pp.95-99
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• 2008

This paper proposes a new minimal resource high-level synthesis algorithm for low power design automation. The proposed algorithm executes an efficient approach to minimize the power consumption of the functional units in a circuit during the high level synthesis. In this paper, we visit all control steps one by one to reduce the switching activity in CDFG. The register sharing algorithm determines the minimum register after the life time analysis of all variable. According to property of input signal for functional unit, the proposed method visits all control step one by one and determines the resource allocation with minimal power consumption at each control step in a greedy fashion. The effect of the proposed algorithm has been proved through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low rover.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.55-65
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• 2004

In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

• Journal of Broadcast Engineering
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• v.11 no.3 s.32
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• pp.326-335
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• 2006

Design criteria far a block code which guarantees minimized PAPR of the OFDM signals are proposed in this paper. Encoding procedure of the minimum PAPR codes (MPC) is composed of searching a seed codeword, circular shifting the register elements, and determining codeword inversion. It is shown that the PEP is invariant to the circular shift of register elements and codeword inversion. Based on such properties, systematic encoding rule for MPC is proposed. In addition proposed encoding rule can reduced greatly the size of look up table for MPC.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.418-424
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• 2010

Many researchers studied methods for the generation of maximum length pseudo random sequences. Sabater et al. analyzed shrunken sequences which are effectively generated by SG(Shrinking Generator) using CA(Cellular Automata). In this paper we propose a new SG which is called LCSG(LFSR and CA based Shrinking Generator) using an LFSR with control register and CA with generator register. The proposed shrunken sequences generated by LCSG have longer periods and high complexities than the shrunken sequences generated by the known method. And we analyze the generated sequences using LCSG.