• Journal of IKEEE
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• v.13 no.1
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• pp.87-93
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• 2009

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.865-868
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• 2001

We designed and fabricated a planner-type thermoelastic microactuator with a latch-up operation for optical switching. Latch-up actuation is prerequisite to implement an optical switch with low power consumption and high reliability. The proposed microactuator consists of four cantilever-shaped thermal actuators, four displacement linkages, two shallow arch-shaped leaf springs, a mobile shuttle mass with a micromirror, and four elastic boundaries. The structural layer of the planar microactuator is phosphorous-doped 12$\mu\textrm{m}$-thick polysilicon, and the sacrificial layer is LTO(Low Temperature Oxide) of 3$\mu\textrm{m}$thickness. The displacement of actuator is as large as 3$\mu\textrm{m}$when the length of actuation bar is 100$\mu\textrm{m}$in length at 5V input voltage. The proposed microactuators have advantages of easy assembly with other optical component by way of fiber alignment in the substrate plane, and its fabrication process features simplicity while retaining batch-fabrication economy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.3079-3084
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• 2014

When an integrated circuit device is burned out under high-intense radiation and device-level simulation that usually requires manufacturer's proprietary information is not available, experimental conformation of a failure mechanism is often the only choice. To distinguish Latchup from other causes experimentally, a new combination of multiple techniques have been developed and demonstrated. Power supply circumvention, hot-spot monitoring using an infrared camera, and supply current monitoring techniques were implemented for the conformation of the Latchup.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.898-907
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• 1992

This paper deals with a detailed analysis of CMOS latch up dependancies on the layout and geo-metrical demensions on the mask using same materials and same processes. For this purpose, six different layout models depending upon the N+ / P+ spacing and three different guard ring models have been gesigned, fabricated, and tested. As a result, common emitter current gain, shunt resistance, and holeing current versus N+/P+ spacing have been measured and analyzed experimentally. Also the fact that guard ring is sffective in reducing the latchup possibility has been verified through this study.

• Journal of IKEEE
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• v.26 no.1
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• pp.119-123
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• 2022

This paper propose a new ESD protection device suitable for 12V class applications by adding a self-biasing structure to an ESD protection device with high holding voltage due to additional parasitic bipolar BJT. To verify the operating principle and electrical characteristics of the proposed device, current density simulation and HBM simulation were performed using Synopsys' TCAD Simulation, and the operation of the additional self-biasing structure was confirmed. As a result of the simulation, it was confirmed that the proposed ESD protection device has a higher level of holding voltage compared to the existing ESD protection device. It is expected to have high area efficiency due to the dual structure and sufficient latch-up immunity in 12V-class applications.

• Journal of IKEEE
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• v.12 no.4
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• pp.255-262
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• 2008

In this paper, we proposed the novel IGBT with an additional n-type MOS structure to achieve the improved trade-off between turn-off and on-state voltage drop(Vce(sat)). These low on-resistance and the fast switching characteristics of the proposed IGBT are caused by an enhanced electron current injection efficiency which is caused by additional n-type MOS structure. In the simulation result, the proposed IGBT has the lower on state voltage of 2.65V and the shorter turn-off time of 4.5us than those of the conventional IGBT(3.33V, 5us).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.6
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• pp.597-602
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• 2008

This paper examines the damage effect and delay time of CMOS integrated circuits device with coupling caused by high power microwaves. The waveguide and magnetron was employed to study the influence of high power micro-waves on CMOS inverters. The CMOS inverters were composed of a LED circuit for visual discernment. Also CMOS inverters broken by high power microwave is observed with supply current and delay time. When the power supply current was increased 2.14 times for normal current at 9.9 kV/m, the CMOS inverter was broken by latch-up. Three different types of damage were observed by microscopic analysis: component, onchipwire, and bondwire destruction. Based on the results, CMOS inverters can be applied to database to elucidate the effects of microwaves on electronic equipment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.793-798
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• 2016

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).