• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• The Journal of the Korea Contents Association
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• v.11 no.11
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• pp.91-101
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• 2011

This research aims to suggest web-based 3D face modeling system for hairline modification surgery. As public interests in beauty regarding face escalate with era of wide persoanl mobile smart iCT devices, need for medical information system is urgent and increasing demand. This research attempted to build 3D facing modeling library deploying conventional technology and proprietary software available. Implications from the our experiment found that problems and requirement for developing new web based standard. We suggest new system from our experiment and literature review regarding relevant technologies. Main features of our suggested systems is based on studies regarding hair loss treatment such as medical science, beauty studies and information technology. This system processes input images of 2D frontal and profile pictures of face into 3D face modeling with mesh-data. The mesh data is compatible with web standard technology including SVG and Canvas Tag supported natively by HTML5.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• Journal of the Korea Society for Simulation
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• v.17 no.1
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• pp.43-52
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• 2008

The High Level Architecture(HLA) is the IEEE 1516 standard for interoperation between heterogeneous simulators which are developed with different languages and platforms. Run-Time Infrastructure(RTI) is a software which implements the HLA Interface Specification. With the development of time management service of RTI, it is necessary to consider an efficient design approach and an algorithm of Greatest Available Logical Time(GALT) computation. However, many time management services of existing RTIs have difficulty in modification and extension. Although some RTIs avoid this difficulty through modular design, they comply with not IEEE 1516 HLA/RTI but HLA 1.3. In addition, a lot of RTIs made use of well-known Mattern's algorithm for GALT computation. However, Mattern's algorithm has a few limitations for applying to IEEE 1516 HLA/RTI. This paper proposes a modular design and an implementation of time management service for IEEE 1516 HLA/RTI. We divided th time management service module into two sub-modules: a TIME module and a GALT module and used Mattern's algorithm improved for IEEE 1516 HLARTI. The paper also contains several experimental results in order to evaluate our time management service module.

• The Journal of the Korea Contents Association
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• v.13 no.4
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• pp.8-16
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• 2013

Active studies are under way on telemedicine and medical support based on mobile devices in order to vitalize U-Healthcare. Especially when the medical law is revised to allow a remote prescription system, studies on a mobile prescription system will rapidly increase. And yet since mobile apps have less compatibility due to the nature of mobile platform, there is a restriction that they have to be redeveloped to be compatible with the platform. To compensate this problem, this study designs a mobile web prescription interface by using HLTML5, the standard language of mobile web development and jQuery Mobile, a JavaScript Library. It also adds a feature of converting to a form of standard protocol HL7-based messages to share data with existing hospital information system. This interface makes it possible to be interlocked with the existing hospital information system through the transmission of the HL7 messages. The advantage of the proposed system is that it can be used in various environments since it is independent of mobile platforms and compatible with general computers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1332-1339
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• 2000

This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.1 no.2
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• pp.4-18
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• 2002

In this paper, we propose the new design method for the OFDM based modem that is considerd a standard of wireless communication in indoor environments. We designed a improved FFT/IFFT in order to satisfy a data rate $6{\sim}54$Mbps required homenetworking of high speed and a improved channel equalization circuit using pilot signals for modile environments. And we designed a carrier offset estimator that uses the $tan^{-1}$ circuit to organize a memory structure. All steps are verifed performance through a FPGA and are implemented ASIC to use a standard library cell.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.