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Design of Digital Codec for EPC RFID Protocols Generation 2 Class 1 Codec  

Lee Yong-Joo (연세대학교 전기전자공학과 프로세서연구실)
Jo Jung-Hyeon (연세대학교 전기전자공학과 프로세서연구실)
Kim Hyung-Kyu (연세대학교 전기전자공학과 프로세서연구실)
Kim Sag-Hoon (연세대학교 전기전자공학과 프로세서연구실)
Lee Yong-Surk (연세대학교 전기전자공학과 프로세서연구실)
Abstract
In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.
Keywords
RFID; low power Tag; Digital codec; air protocol; EPC generation 2;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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