• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.6
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• pp.1402-1409
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• 2007

In this paper, we propose various types of AGC algorithms for implementing the OFDM communication systems. For the high-speed packet transmission, in this paper, we assume the OFDM system with relatively long and repeated preambles. We propose the maximum sample value counter for counting the number of maximum sample. In the maximum sample value counter, we use the buffer for the digital signal buffering. Finally, the counting value of the maximum sample value counter controls the gain control signal generator by using gain control table automatically.

• Journal of the Korea Society of Computer and Information
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• v.5 no.4
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• pp.62-68
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• 2000

It was designed a high-speed analog input card that is a important device of ultrasonic testing flaw detector in the middle of non-destructive testing in this Paper. The A/D Board is inquired high-speed sampling rate and fast data acquisition system. This pater shows a design that has a function of Peak- Detection for ultrasonic testing by ISA Bus type and a 50MHz of A/D converter in order to do sampling more than quadruple frequency of transducer frequency.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.842-845
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• 2004

PWM 입력 전압원 반브리지 직류-직류 변환기의 예로 통상적인 스위칭 방법으로 동작시킬 때, 직류 전압원의 단락을 방지하기 위하여 변환기 신호에 데드타임을 삽입한다. 이러한 데드타임은 변환기 시스템의 제어 성능에 좋지 않은 영향을 발생시킨다. 따라서 이 데드타임을 효과적으로 보상하는 것이 필요하다. 또 이 데드타임의 영향을 방지 할 수 있는 최선의 방법으로써 데드타임 최소화 스위칭 방법을 고려할 수도 있다. 본 논문에서는 데드타임 최소화 스위칭 방법의 하나인 아날로그 방법이 아닌 디지털 방법으로 스위칭 방법을 제안하였다. 제안한 스위칭 방법은 SOC를 기반으로 한 Verilog-HDL 언어를 이용하여 PWM전용 컨트롤러를 설계하고, 기존에 문제점으로 PWM 스위칭 발생시 과도기간 동안 턴오프 손실이 발생되어 저하된 효율를 제안된 방법으로 방지하였다.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.12
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• pp.1923-1930
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• 2004

This paper presents digital microflow controllers(DMFC), where a fluidic digital-to-analog converter(DAC) is used to achieve high-linearity, fine-level flow control for applications to precision biomedical dosing systems. The fluidic DAC, composed of binary-weighted flow resistance, controls the flow-rate based on the ratio of the flow resistance to achieve high-precision flow-rate control. The binary-weighted flow resistance has been specified by a serial or a parallel connection of an identical flow resistor to improve the linearity of the flow-rate control, thereby making the flow-resistance ratio insensitive to the size uncertainty in flow resistors due to micromachining errors. We have designed and fabricated three different types of 4-digit DMFC: Prototype S and P are composed of the serial and the parallel combinations of an identical flow resistor, while Prototype V is based on the width-varied flow resistors. In the experimental study, we perform a static test for DMFC at the forward and backward flow conditions as well as a dynamic tests at pulsating flow conditions. The fabricated DMFC shows the nonlinearity of 5.0% and the flow-rate levels of 16(2$^{N}$) for the digital control of 4(N) valves. Among the 4-digit DMFC fabricated with micromachining errors, Prototypes S and P show 27.2% and 27.6% of the flow-rate deviation measured from Prototype V, respectively; thus verifying that Prototypes S and P are less sensitive to the micromachining error than Prototype V.V.

• Bulletin of the Korean Space Science Society
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• 2010.04a
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• pp.37.5-38
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• 2010

경희대학교 우주탐사학과에서는 우주공간 탐사를 위해 Trio(TRiplet Ionospheric Observatory)-CINEMA(Cubesat for Ions, Neutrals, Electrons and MAgnetic fields)로 명명된 초소형 위성을 개발하고 있다. 과학임무는 지구 저궤도에서 고에너지 입자를 관측하는 것이며, 이를 위해 고에너지 (2~300keV) 입자 검출기와 자기장 측정기가 탑재된다. 저에너지 입자 검출기 시스템인 STEIN(SupraThermal Electrons, Ions, Neutrals)은 $1\times4$ Array의 개선된 실리콘 검출기와 이온, 전자, 중성입자를 분리할 수 있는 정전장 편향기, 그리고 신호를 처리하는 전자회로로 구성되어있다. 설계된 전자회로는 매우 작은 검출기 기판, 아날로그 기판과 디지털 기판으로 이루어져 있고, 475mW 이하의 저 전력으로 동작한다. 또한 2~100keV의 에너지를 1keV이하의 해상도로 30,000event/sec/pixel 까지 관측 할 수 있도록 회로를 설계하였다. 센서로 들어온 입자로 인해 발생한 펄스의 신호는 4개의 아날로그 회로가 담당하게 되는데, Folded cascode amplifier를 배치하여 증폭률을 높인 Charge sensitive amplifier를 통해 신호를 증폭하고, $2{\mu}s$ unipolar gaussian shaping amplifier를 통해 읽기 쉽게 처리된 신호를 상한파고선별기와 하한파고 선별기를 통해 유효 값 여부를 판단하고, 피크 검출기를 통해 피크의 타이밍을 측정한 뒤 신호를 아날로그-디지털 변환 회로를 통하여 8bit의 값으로 나타내어, 입자들의 Spectrum을 측정하게 된다. 크기와 소비전력이 적음에도 검출성능이 우수하기 때문에 이 시스템은 향후 우주탐사 시스템에 있어 매우 중요한 역할을 수행 할 것으로 생각한다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.421-422
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• 2012

본 논문은 넓은 범위에서 변화하는 입력 전압과 출력 전류 조건에서 동작하는 공진형 직류-직류 컨버터의 디지털 제어기 해석 및 설계에 대해 기술한다. LLC 직렬 공진형 컨버터의 전력 변환단 동 특성을 기반으로 디지털 제어기를 해석 및 설계하고, DSP 기능을 내장한 16 비트 마이크로 컨트롤러를 이용하여 제어기를 구현한다. 개발된 디지털 제어기를 150W 공진형 컨버터 보드에 적용하여 설계 이론을 실험적으로 검증하고, 종래의 아날로그 제어기를 적용한 컨버터와의 장단점과 동 특성을 비교 검증한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.65-71
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• 2005

Physical signals generated in the real world are transformed into electrical signals through sensors and fed into electronic circuits. The electrical signals input to electronic circuits are in analog form, thus they must be converted to digital signals using an ADC(Analog-Digital Converter) for digital processing. Signal processing circuits and ADCs that are to be integrated on a single chip together with silicon micro sensors should be designed to have less silicon area and less power consumption. This paper proposed a charge redistribution ADC which reduces silicon area considerably. The proposed method achieves 8 bit conversion by performing 4-bit conversion twice. It reduced the area of capacitor array, which takes most of the ADC area, by 1/16 when compared to a conventional method. Though it uses twice the number of clocks as a conventional method, it would be appropriate to be integrated with a silicon pressure sensor on a single chip since it does not demand high conversion rate.